AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 30

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

DETAILED FUNCTIONS
Slave Bus Interface Unit
The slave bus interface unit (BIU) controls all accesses
to the PCI configuration space, the Control and Status
Registers (CSR), the Bus Configuration Registers
Slave Configuration Transfers
The host can access the PCnet-PCI II controller PCI
configuration space with a configuration read or write
command. The PCnet-PCI II controller will assert
DEVSEL during the address phase when IDSEL is as-
serted, AD[1:0] are both ZERO, and the access is a con-
figuration cycle. AD[7:2] select the DWord location in the
configuration space. The PCnet-PCI II controller ig-
nores AD[10:8], because it is a single function device.
AD[31:11] are don’t care.
The active bytes within a DWord are determined by the
byte enable signals. 8-bit, 16-bit and 32-bit transfers are
supported. DEVSEL is asserted two clock cycles after
the host has asserted FRAME. All configuration cycles
are of fixed length. The PCnet-PCI II controller will as-
sert TRDY on the 4th clock of the data phase.
The PCnet-PCI II controller does not support burst
transfers for access to configuration space. When the
30
C[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
AD31
AMD
Don’t care
Command
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write Invalidate
—
AD11
AD10
Don’t care
Table 2. Slave Commands
—
P R E L I M I N A R Y
Use
Not Used
Not Used
Read of CSR, BCR and APROM
Write to CSR, BCR and APROM
Memory Mapped I/O Read of CSR, BCR and APROM
Read of the Expansion ROM
Memory Mapped I/O Write of CSR, BCR and APROM
Dummy Write to the Expansion ROM
Read of the Configuration Space
Write to the Configuration Space
Aliased to Memory Read
Not Used
Aliased to Memory Read
Aliased to Memory Write
Am79C970A
AD8
(BCR), the Address PROM (APROM) locations and the
Expansion ROM. The table below shows the response
of the PCnet-PCI II controller to each of the PCI com-
mands in slave mode.
host keeps FRAME asserted for a second data phase,
the PCnet-PCI II controller will disconnect the transfer.
When the host tries to access the PCI configuration
space while the automatic read of the EEPROM after
H_RESET is on-going, the PCnet-PCI II controller will
terminate the access on the PCI bus with a disconnect/
retry response.
The PCnet-PCI II controller supports fast back-to-back
transactions to different targets. This is indicated by the
Fast Back-To-Back Capable bit (PCI Status register,
bit 7), which is hardwired to ONE. The PCnet-PCI II con-
troller is capable of detecting a configuration cycle even
when its address phase immediately follows the data
phase of a transaction to a different target without any
idle state in-between. There will be no contention on
the DEVSEL, TRDY and STOP signals, since the
PCnet-PCI II controller asserts DEVSEL on the second
clock after FRAME is asserted (medium timing).
AD7
DWord index
—
AD2
AD1
0
AD0
0