AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 118

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

0
CSR4: Test and Features Control
Bit
31–16 RES
15
14
118
AMD
DMAPLUS
EN124
Name
RES
and should treat the read value
as undefined.
Reserved location. The default
value of this bit is a ZERO. Writ-
ing a ONE to this bit has no effect
on device function. If a ONE is
written to this bit, then a ONE will
be read back. Existing drivers
may write a ONE to this bit for
compatibility, but new drivers
should write a ZERO to this bit
and should treat the read value
as undefined.
Description
Certain bits in CSR4 indicate the
cause of an interrupt. The regis-
ter is designed so that these
indicator bits are cleared by writ-
ing ONEs to those bit locations.
This means that the software can
read CSR4 and write back the
value just read to clear the
interrupt condition.
Reserved locations. Written as
ZEROs and read as undefined.
Enable CSR124 access. Setting
EN124 to ONE allows the user to
write to bits in CSR124 which
enable
(GPSIEN, bit 4) and Runt Packet
Accept mode (RPA, bit 3). Once
these bits are accessed EN124
must be cleared back to ZERO.
Read/Write accessible always.
EN124 is cleared by H_RESET
or S_RESET and is unaffected
by setting the STOP bit.
In order to set EN124, it must be
written with a ONE during the first
write access to CSR4 after
H_RESET or S_RESET. Once a
ZERO is written to this bit
position, EN124 cannot be set
until after the PCnet-PCI II
controller is reset by H_RESET
or S_RESET.
When DMAPLUS is set to ONE,
the DMA Burst Transfer Counter
in
DMAPLUS is cleared to ZERO,
the counter is enabled.
DMAPLUS should be set to ONE
when the PCnet-PCI II controller
is used in a PCI bus application.
Read/Write accessible always.
DMAPLUS
H_RESET or S_RESET and is
CSR80
the
is
is
GPSI
disabled.
cleared
interface
P R E L I M I N A R Y
Am79C970A
by
If
13
12
11 APAD_XMT
10 ASTRP_RCV
DPOLL
TIMER
unaffected
STOP bit.
Enable Bus Activity Timer. If
TIMER is set to ONE, the Bus Ac-
tivity Timer (CSR82) is enabled.
If TIMER is cleared, the Bus Ac-
tivity Timer is disabled.
TIMER should stay at its default
value
PCnet-PCI II controller is used in
a PCI bus application.
Read/Write accessible always.
TIMER is cleared by H_RESET
or S_RESET and is unaffected
by setting the STOP bit.
Disable
DPOLL is set, the Buffer Man-
agement Unit will disable trans-
mit polling. If DPOLL is cleared,
automatic transmit polling is en-
abled. If DPOLL is set, the TDMD
bit in CSR0 must be set in order
to initiate a manual poll of a
transmit descriptor. transmit de-
scriptor polling will not take place
if TXON is cleared.
Read/Write accessible always.
DPOLL is cleared by H_RESET
or S_RESET and is unaffected
by setting the STOP bit.
Auto Pad Transmit. When set,
APAD_XMT enables the auto-
matic padding feature. Transmit
frames will be padded to extend
them to 64 bytes including FCS.
The FCS is calculated for the en-
tire frame including pad, and
appended
APAD_XMT will override the pro-
gramming of the DXMTFCS bit
(CSR15, bit 3) and of the
ADD_FCS/NO_FCS bit (TMD1,
bit 29).
Read/Write accessible always.
APAD_XMT
H_RESET or S_RESET and
is unaffected by setting the
STOP bit.
Auto Strip Receive. When set,
ASTRP_RCV enables the auto-
matic pad stripping feature. The
pad and FCS fields will be
stripped from receive frames and
not placed in the FIFO.
Read/Write accessible always.
ASTRP_RCV
H_RESET or S_RESET and
is unaffected by setting the
STOP bit.
of
Transmit
ZERO
after
by
is
is
setting
cleared
cleared
when
Polling.
the
pad.
the
the
by
by
If