AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 135

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

CSR76: Receive Descriptor Ring Length
Bit
31–16 RES
15–0 RCVRL
CSR78: Transmit Descriptor Ring Length
Bit
31–16 RES
15–0 XMTRL
Name
Name
transmit descriptor. This counter
interprets the value in CSR78 as
pointing to the first descriptor. A
counter value of ZERO corre-
sponds to the last descriptor in
the ring.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Receive Descriptor Ring Length.
Contains the two’s complement
of the receive descriptor ring
length. This register is initialized
during the PCnet-PCI II controller
initialization routine based on the
value in the RLEN field of the in-
itialization block. However, the
ring length can be programmed
to any value from 1 to 65535 by
writing directly to this register.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Transmit
Length.
complement of the transmit de-
scriptor ring length. This register
is initialized during the PCnet-
PCI II controller initialization rou-
tine based on the value in the
TLEN field of the initialization
block. However, the ring length
can be programmed to any value
from 1 to 65535 by writing directly
to this register.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Contains
Descriptor
accessible
accessible
accessible
the
P R E L I M I N A R Y
two’s
Ring
only
only
only
Am79C970A
CSR80: DMA Transfer Counter and FIFO
Watermark Control
Bit
31–16 RES
15–14 RES
13–12RCVFW[1:0]
11–10XMTSP[1:0]
Table 26. Receive Watermark Programming
RCVFW[1:0]
Name
00
01
10
11
Description
Reserved locations. Written as
ZEROs and read as undefined.
Reserved locations. Read as
ONEs and written as ZEROs. Ac-
cessible only when either the
STOP or the SPND bit is set.
Receive
RCVFW specifies the number of
bytes which must be present in
the receive FIFO (once the frame
has been verified as a non-runt)
before receive DMA is re-
quested. If the network interface
is operating in half-duplex mode,
at least 64 bytes or a complete
frame must be received in order
for a receive DMA to start. This
effectively avoids having to react
to receive frames which are runts
or suffer a collision during the slot
time (512 bit times). If the Runt
Packet Accept feature is enabled
or if the network interface is oper-
ating in full-duplex mode, receive
DMA will be requested as soon
as either the Receive FIFO Wa-
termark is reached, or a com-
plete valid receive frame is
detected (regardless of length). If
the EADI interface is active and
the Runt Packet Accept feature is
enabled or the network interface
is
mode, RCVFW must not be
programmed to 00b to allow
enough time to reject the frame.
Read/Write
when either the STOP or the
SPND bit is set. RCVFW is set
to a value of 01b (64 bytes) after
H_RESET or S_RESET and
is unaffected by setting the
STOP bit.
Transmit Start Point. As soon as
the number of bytes in the trans-
mit FIFO reaches the XMTSP
value, the PCnet-PCI II controller
operating
Bytes Received
FIFO
Reserved
accessible
128
16
64
in
Watermark.
full-duplex
AMD
only
135