AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 217

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

CSR15: Mode
CSR58: Software Style
CSR80: DMA Transfer Counter and FIFO
Threshold Control
CSR82: Bus Activity Timer
CSR88: Chip ID Lower
CSR89: Chip ID Upper
CSR100: Bus Timeout
CSR112: Missed Frame Count
Bus Configuration Registers
BCR2: Miscellaneous Configuration
New bit: MPMODE (bit 1), Magic Packet Mode.
Was reserved location, read and written as ZERO.
New bit: SPND (bit 0), Suspend. Was reserved
location, read and written as ZERO.
PORTSEL (bits 8–7), Network Port Select. New
option, value of 10b selects GPSI mode.
New bit: APERREN (bit 10), Advanced Parity Error
Handling Enable. Was reserved location, read and
written as ZERO.
SWSTYLE (bits 7–0), Software Style. New option,
value of THREE selects new PCnet-PCI controller
style that reorders 32-bit descriptor entries to allow
burst accesses.
RCVFW (bits 13–12), Receive FIFO Watermark.
Decoding adjusted for the larger FIFO size.
XMTSP (bits 11–10), Transmit Start Point. Decod-
ing adjusted for the larger FIFO size.
XMTFW (bits 9–8), Transmit FIFO Watermark. De-
coding adjusted for the larger FIFO size.
DMATC (bits 7–0), DMA Transfer Count.
Function of the counter is optimized for the PCI
bus environment.
DMABAT (bits 15–0), DMA Bus Activity Timer.
Function of the counter is optimized for the PCI
bus environment.
New value: 1003h. Was 0003h.
New value : 0262h. Was 0243h.
Default value now 0600h (153.6 s) to adjust to
the larger FIFO size. Default value was 0200h
(51.2 s).
Counter is stopped while the device is in
suspend mode
New bit: INTLEVEL (bit 7), Interrupt Level. Was
reserved location, read and written as ZERO.
New bit: DXCVRCTL (bit 5), DXCVR Control. Was
reserved location, read and written as ZERO.
New bit: DXCVRPOL (bit 4), DXCVR Polarity. Was
reserved location, read and written as ZERO.
Am79C970A
BCR4: Link Status LED
BCR5: LED1 Status
BCR6: LED2 Status
BCR7: LED3 Status
BCR9: Full Duplex Control
BCR16: I/O Base Address Lower
New bit: EADISEL (bit 3), EADI Select. Was re-
served location, read and written as ZERO.
Register is now programmable through
the EEPROM
New bit: MPSE (bit 9), Magic Packet Status En-
able. Was reserved location, read and written as
ZERO.
New bit: FDLSE (bit 8), Full Duplex Link Status
Enable. Was reserved location, read and written as
ZERO.
COLE (bit 0), Collision Status Enable. Corrected
behavior of function. LED will not light up due to
SQE test collision signal.
Register is now programmable through the
EEPROM
New bit: MPSE (bit 9), Magic Packet Status En-
able. Was reserved location, read and written as
ZERO.
New bit: FDLSE (bit 8), Full Duplex Link Status
Enable. Was reserved location, read and written as
ZERO.
COLE (bit 0), Collision Status Enable. Corrected
behavior of function. LED will not light up due to
SQE test collision signal.
New register. Was reserved location, the settings
of the register have no effect on the operation of
the device.
Register is now programmable through
the EEPROM
New bit: MPSE (bit 9), Magic Packet Status En-
able. Was reserved location, read and written as
ZERO.
New bit: FDLSE (bit 8), Full Duplex Link Status
Enable. Was reserved location, read and written as
ZERO.
COLE (bit 0), Collision Status Enable. Corrected
behavior of function. LED will not light up due to
SQE test collision signal.
New register. Was reserved location, read and
written as ZERO.
This register is no longer programmable through
the EEPROM. The register is reserved and has no
effect on the operation of the device. It is only used
in the PCnet-32.
AMD
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