AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 130

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

CSR40: Current Receive Byte Count
Bit
31–16 RES
15–12 RES
11–0
CSR41: Current Receive Status
Bit
31–16 RES
15–0
CSR42: Current Transmit Byte Count
Bit
31–16 RES
15–12 RES
11–0
15–0
130
AMD
CRBC
CRST
CXBC
CXST
Name
Name
Name
Description
Reserved locations. Written as
ZEROs and read as undefined.
Reserved locations. Read and
written as ZEROs.
Current Receive Byte Count.
This field is a copy of the BCNT
field of RMD1 of the current
receive descriptor.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Current Receive Status. This
field is a copy of bits 31–16
of
receive descriptor.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Reserved locations. Read and
written as ZEROs.
Current Transmit Byte Count.
This field is a copy of the BCNT
field of TMD1 of the current
transmit descriptor.
Current Transmit Status. This
field is a copy of bits 31–16
of
transmit descriptor.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
RMD1
TMD1
of
of
accessible
accessible
accessible
the
the
P R E L I M I N A R Y
current
current
only
only
only
Am79C970A
CSR44: Next Receive Byte Count
Bit
31–16 RES
15–12 RES
11–0
CSR45: Next Receive Status
Bit
31–16 RES
15–0
CSR46: Poll Time Counter
Bit
31–16 RES
15–0
NRBC
NRST
POLL
Name
Name
Name
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Reserved locations. Read and
written as ZEROs.
Next Receive Byte Count. This
field is a copy of the BCNT
field of RMD1 of the next
receive descriptor.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Next Receive Status. This field is
a copy of bits 31–16 of RMD1 of
the next receive descriptor.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Poll
counter
the PCnet-PCI II
microcode
trigger the descriptor ring polling
operation of the PCnet-PCI II
controller.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Time
is
and
accessible
accessible
accessible
incremented
Counter.
is
controller
used
This
only
only
only
by
to