AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 163

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

RMD0
Bit
31–0 RBADR
RMD1
Bit
31
30
29
28
27
FRAM
OFLO
Name
Name
OWN
ERR
CRC
Description
Receive Buffer address. This
field contains the address of the
receive buffer that is associated
with this descriptor.
Description
This bit indicates whether the
descriptor entry is owned by
the host (OWN = 0) or
the
(OWN = 1). The PCnet-PCI II
controller clears the OWN bit af-
ter filling the buffer that the de-
scriptor points to. The host sets
the OWN bit after emptying the
buffer. Once the PCnet-PCI II
controller or host has relin-
quished ownership of a buffer, it
must not change any field in the
descriptor entry.
ERR is the OR of FRAM, OFLO,
CRC, BUFF or BPE. ERR is set
by the PCnet-PCI II controller
and cleared by the host.
Framing error indicates that the
incoming
non-integer multiple of eight bits
and there was an FCS error. If
there was no FCS error on the in-
coming frame, then FRAM will
not be set even if there was a
non-integer multiple of eight bits
in the frame. FRAM is not valid in
internal loopback mode. FRAM is
valid only when ENP is set and
OFLO is not. FRAM is set by
the PCnet-PCI II controller and
cleared by the host.
Overflow error indicates that the
receiver has lost all or part of the
incoming frame, due to an inabil-
ity to move data from the receive
FIFO into a memory buffer before
the internal FIFO overflowed.
OFLO is valid only when ENP
is not set. OFLO is set by
the PCnet-PCI II controller and
cleared by the host.
CRC indicates that the receiver
has detected a CRC (FCS) error
on the incoming frame. CRC is
valid only when ENP is set and
OFLO is not. CRC is set by
PCnet-PCI
frame
II
contains
controller
P R E L I M I N A R Y
Am79C970A
by
a
26
25
24
23
BUFF
ENP
STP
BPE
the PCnet-PCI II controller and
cleared by the host.
Buffer error is set any time the
PCnet-PCI II controller does not
own the next buffer while data
chaining a received frame. This
can occur in either of two ways:
1. The OWN bit of the next
2. FIFO overflow occurred be-
If a Buffer Error occurs, an
Overflow Error may also occur in-
ternally in the FIFO, but will not
be reported in the descriptor
status entry unless both BUFF
and OFLO errors occur at the
same time. BUFF is set by the
PCnet-PCI
cleared by the host.
Start of Packet indicates that this
is the first buffer used by the
PCnet-PCI II controller for this
frame. If STP and ENP are both
set to ONE, the frame fits into a
single buffer. Otherwise, the
frame is spread over more than
one
(CSR3, bit 5) is cleared to ZERO,
STP is set by the PCnet-PCI II
controller and cleared by the
host. When LAPPEN is set to
ONE, STP must be set by
the host.
End of Packet indicates that
this is the last buffer used by
the PCnet-PCI II controller for
this frame. It is used for data
chaining buffers. If both STP and
ENP are set, the frame fits into
one buffer and there is no data
chaining. ENP is set by the
PCnet-PCI
cleared by the host.
Bus Parity Error is set by the
PCnet-PCI II controller when a
parity error occurred on the bus
interface during a data transfers
to a receive buffer. BPE is valid
only when ENP, OFLO or BUFF
are set. The PCnet-PCI II control-
ler will only set BPE when the ad-
vanced parity error handling is
enabled by setting APERREN
(BCR20, bit 10) to ONE. BPE is
buffer is ZERO.
fore
controller was able to read
the
next descriptor.
buffer.
OWN
the
II
II
When
controller
controller
PCnet-PCI
bit
AMD
LAPPEN
of
163
and
and
the
II