AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 77

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

current descriptor. The OWN bit(s) in the subsequent
descriptor(s) will be cleared until the STP (the next
frame) is found.
Loss of Carrier
When operating in half-duplex mode, a loss of carrier
condition will be reported if the PCnet-PCI II controller
cannot observe receive activity whilst it is transmitting
on the AUI or GPSI port. In AUI mode, after the
PCnet-PCI II controller initiates a transmission it will ex-
pect to see data “looped-back” on the DI pair. This will
internally generate a “carrier sense”, indicating that the
integrity of the data path to and from the MAU is intact,
and that the MAU is operating correctly. This “carrier
sense” signal must be asserted before the last bit is
transmitted on DO . If “carrier sense” does not become
active in response to the data transmission, or becomes
inactive before the end of transmission, the loss of car-
rier (LCAR) error bit will be set in TMD2 after the frame
has been transmitted. The frame will not be retried on
the basis of an LCAR error. In GPSI mode, LCAR will
be asserted if RXEN does not go active during
the transmission.
When the 10BASE-T port is selected, LCAR will be re-
ported for every frame transmitted while the network in-
terface is in the Link Fail state.
Late Collision
A late collision will be reported if a collision condition oc-
curs after one slot time (512 bit times) after the transmit
process was initiated (first bit of preamble commenced).
The PCnet-PCI II controller will abandon the transmit
process for that frame, set Late Collision (LCOL) in the
associated TMD2, and process the next transmit frame
in the ring. Frames experiencing a late collision will not
be retried. Recovery from this condition must be per-
formed by upper layer software.
SQE Test Error
During the inter packet gap time following the comple-
tion of a transmitted message, the AUI CI pair is as-
serted by some transceivers as a self-test. The integral
Manchester Encoder/Decoder will expect the SQE Test
Message (nominal 10 MHz sequence) to be returned via
the CI pair within a 40 network bit-time period after DI
goes inactive (this does not apply if the 10BASE-T port
is selected). If the CI input is not asserted within the 40
network bit-time period following the completion of
transmission, then the PCnet-PCI II controller will set
the CERR bit in CSR0. In GPSI mode, CLSN must be
asserted after the transmission or otherwise CERR will
be set. CERR will be asserted in 10BASE-T mode after
transmit if T-MAU is in Link Fail state. CERR will never
cause INTA to be activated. It will, however, set the ERR
bit CSR0.
P R E L I M I N A R Y
Am79C970A
Receive Operation
The receive operation and features of the PCnet-PCI II
controller are controlled by programmable options. The
PCnet-PCI II controller offers a 256-byte receive FIFO
to provide frame buffering for increased system latency,
automatic flushing of collision fragments (runt packets),
automatic receive pad stripping and a variety of address
match options.
Receive Function Programming
Automatic pad field stripping is enabled by setting the
ASTRP_RCV bit in CSR4. This can provide flexibility
in the reception of messages using the 802.3
frame format.
All receive frames can be accepted by setting the PROM
bit in CSR15. Acceptance of unicast and broadcast
frames can be individually turned off by setting the
DRCVPA or DRCVBC bits in CSR15. The Physical Ad-
dress register (CSR12 to CSR14) stores the address
the PCnet-PCI II controller compares to the destination
address of the incoming frame for a unicast address
match. The Logical Address Filter register (CSR8 to
CSR11) serves as a hash filter for multicast
address match.
The point at which the BMU will start to transfer data
from the receive FIFO to buffer memory is controlled by
the RCVFW bits in CSR80. The default established dur-
ing H_RESET is 01b which sets the watermark flag at 64
bytes filled.
For test purposes, the PCnet-PCI II controller can be
programmed to accept runt packets by setting RPA
in CSR124.
Address Matching
The PCnet-PCI II controller supports three types of ad-
dress matching: unicast, multicast, and broadcast. The
normal address matching procedure can be modified by
programming three bits in CSR15, the mode register
(PROM, DRCVPA, and DRCVBC).
If the first bit received after the start of frame delimiter
(the least significant bit of the first byte of the destination
address field) is 0, the frame is unicast, which indicates
that the frame is meant to be received by a single node.
If the first bit received is 1, the frame is multicast, which
indicates that the frame is meant to be received by a
group of nodes. If the destination address field contains
all ONEs, the frame is broadcast, which is a special type
of multicast. Frames with the broadcast address in the
destination address field are meant to be received by all
nodes on the local area network.
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