AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 46

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

The following figure shows two non-burst write transac-
tions. The first transaction has two wait states. The tar-
get inserts one wait state by asserting DEVSEL one
clock late and another wait state by also asserting TRDY
Basic Burst Write Transfer
The PCnet-PCI II controller supports burst mode for all
bus master write operations. The burst mode must be
enabled by setting BWRITE (BCR18, bit 5). To allow
burst transfers in descriptor write operations, the
PCnet-PCI II controller must also be programmed to use
SWSTYLE THREE (BCR20, bits 7–0). All PCnet-PCI II
controller burst write transfers are of the PCI command
type Memory Write (type 7). AD[1:0] will both be ZERO
during the address phase indicating a linear burst order.
The byte enable signals indicate the byte lanes that
have valid data.
46
AMD
DEVSEL
FRAME
TRDY
IRDY
C/BE
REQ
GNT
CLK
PAR
AD
1
DEVSEL is sampled
2
ADDR
0111
Figure 15. Non-Burst Write Transfer
3
PAR
P R E L I M I N A R Y
4
Am79C970A
DATA
BE
5
one clock late. The second transaction shows a zero
wait state write cycle. The target asserts DEVSEL and
TRDY in the same cycle as the PCnet-PCI II controller
asserts IRDY.
The PCnet-PCI II controller will always perform a single
burst write transaction per bus mastership period,
where transaction is defined as one address phase and
one or multiple data phases. The PCnet-PCI II controller
supports zero wait state write cycles except with the
case of descriptor write transfers. (See the section
“Descriptor DMA Transfers” for the only exception.) It
asserts IRDY immediately after the address phase and
at the same time starts sampling DEVSEL. FRAME is
deasserted when the next to the last data phase
is completed.
PAR
6
7
ADDR
0111
8
DATA
PAR
BE
9
PAR
10
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