AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 65

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

If a receive buffer does not end on a DWord boundary,
the PCnet-PCI II controller will perform a non-DWord
write on the last transfer to the buffer. The following fig-
ure shows the final three FIFO DMA transfers to a re-
ceive buffer. Since there were only nine bytes of space
left in the receive buffer, the PCnet-PCI II controller
burst three data phases. The first two data phases write
a full DWord, the last one only writes a single byte.
Note that the PCnet-PCI II controller will always perform
a DWord transfer as long as it owns the buffer space,
In a PCI bus application the PCnet-PCI II controller
should be set up to have the length of a bus mastership
period be controlled only by the PCI Latency Timer. The
Timer bit (CSR4, bit 13) should remain at its default
value of ZERO so that the DMA Bus Activity Timer
(CSR82) is not enabled. The DMA Transfer Counter
(CSR80) should be disabled by setting DMAPLUS
(CSR4, bit 14) to ONE. In this mode, the PCnet-PCI II
controller will continue transferring FIFO data until the
DEVSEL
FRAME
TRDY
IRDY
C/BE
REQ
GNT
CLK
PAR
Figure 31. FIFO Burst Write At End Of Unaligned Buffer
AD
1
DEVSEL is sampled
2
P R E L I M I N A R Y
0111
ADD
Am79C970A
3
DATA
PAR
even when there are less then four bytes to write. For ex-
ample, if there is only one byte left for the current receive
frame, the PCnet-PCI II controller will write a full DWord,
containing the last byte of the receive frame in the least
significant byte position (BSWP is cleared to ZERO,
CSR3, bit 2). The content of the other three bytes is
undefined. The message byte count in the receive
descriptor always reflects the exact length of the
received frame.
4
transmit FIFO is filled to its high threshold (read trans-
fers) or the receive FIFO is emptied to its low threshold
(write transfers), or the PCnet-PCI II controller is
preempted, and the PCI Latency Timer is expired. The
host should use the values in the PCI MIN_GNT and
MAX_LAT registers to determine the value for the PCI
Latency Timer.
0000
DATA
PAR
5
DATA
1110
PAR
6
PAR
7
19436A-34
AMD
65