AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 107

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

The PCI Device ID register is located at offset 02h in the
PCI Configuration Space. It is read only.
PCI Command Register (Offset 04h)
The PCI Command register is a 16-bit register used to
control the gross functionality of the PCnet-PCI II con-
troller. It controls the PCnet-PCI II controller’s ability to
generate and respond to PCI bus cycles. To logically
disconnect the PCnet-PCI II controller device from all
PCI bus cycles except Configuration cycles, a value of
ZERO should be written to this register.
The PCI Command register is located at offset 04h in the
PCI Configuration Space. It is read and written by
the host.
Bit
15–10 RES
9
8
7
6
SERREN
PERREN
FBTBEN
ADSTEP
Name
Description
Reserved locations. Read as
ZEROs, write operations have
no effect.
Fast Back-to-Back Enable. Read
as ZERO, write operations have
no effect. The PCnet-PCI II con-
troller will not generate Fast
Back-to-Back cycles.
SERR enable. Controls the as-
sertion of the SERR pin. SERR is
disabled
cleared. SERR will be asserted
on detection of an address parity
error and if both SERREN and
PERREN (bit 6 of this register)
are set.
SERREN
H_RESET and is not effected by
S_RESET or by setting the
STOP bit.
Address/data stepping. Read as
ZERO, write operations have
no effect. The PCnet-PCI II
controller
address stepping.
Parity Error Response enable.
Enables the parity error re-
sponse
PERREN is “0” and the PCnet-
PCI II controller detects a parity
error, it only sets the Detected
Parity Error bit in the PCI Status
register. When PERREN is “1”,
the PCnet-PCI II controller as-
serts PERR on the detection of a
data parity error. It also sets the
DATAPERR bit (PCI Status
register, bit 8), when the data
parity error occurred during a
master cycle. PERREN also en-
ables reporting address parity er-
rors through the SERR pin and
when
functions.
does
is
cleared
SERREN
not
P R E L I M I N A R Y
When
Am79C970A
use
by
is
5
4
3
2
1
VGASNOOP
SCYCEN
MEMEN
MWIEN
BMEN
the SERR bit in the PCI
Status register.
PERREN
H_RESET and is not effected by
S_RESET or by setting the
STOP bit.
VGA palette snoop. Read as
ZERO, write operations have
no effect.
Memory Write and Invalidate Cy-
cle enable. Read as ZERO, write
operations have no effect. The
PCnet-PCI II controller only gen-
erates Memory Write cycles.
Special Cycle enable. Read as
ZERO, write operations have
no effect. The PCnet-PCI II
controller ignores all Special
Cycle operations.
Bus Master enable. Setting
BMEN enables the PCnet-PCI II
controller to become a bus mas-
ter on the PCI bus. The host must
set BMEN before setting the INIT
or STRT bit in CSR0 of the
PCnet-PCI II controller.
BMEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
Memory Space access enable.
The PCnet-PCI II controller will
ignore all memory accesses
when MEMEN is cleared. The
host must set MEMEN before
the first memory access to
the device.
For memory mapped I/O, the
host must program the PCI Mem-
ory Mapped I/O Base Address
register with a valid memory ad-
dress before setting MEMEN.
For accesses to the Expansion
ROM, the host must program the
PCI
Address register at offset 30h
with a valid memory address
before setting MEMEN. The
PCnet-PCI II controller will only
respond to accesses to the Ex-
pansion
ROMEN (PCI Expansion ROM
Base Address register, bit 0)
and MEMEN are set to ONE.
Since MEMEN also enables the
memory mapped access to
the PCnet-PCI II controller I/O
resources, the PCI Memory
Mapped I/O Base Address regis-
ter must be programmed with an
Expansion
ROM
is
cleared
ROM
when
AMD
Base
both
107
by