AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 59

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

During descriptor write accesses, only the byte lanes
which need to be written are enabled.
If buffer chaining is used, accesses to the descriptors of
all intermediate buffers consist of only one data transfer
to return ownership of the buffer to the system. When
SWSTYLE (BCR20, bits 7–0) is cleared to ZERO (i.e.
the descriptor entries are organized as 16-bit software
structures), the descriptor access will write a single byte.
When SWSTYLE (BCR20, bits 7–0) is set to ONE, TWO
DEVSEL
FRAME
TRDY
IRDY
C/BE
REQ
GNT
PAR
CLK
AD
1
DEVSEL is sampled
Figure 26. Descriptor Ring Read In Non-Burst Mode
2
0110
MD1
3
PAR
P R E L I M I N A R Y
4
0000
Am79C970A
DATA
5
or THREE (i.e. the descriptor entries are organized as
32-bit software structures), the descriptor access will
write a single word. On all single buffer transmit or re-
ceive descriptors, as well as on the last buffer in chain,
writes to the descriptor consist of two data transfers. The
first one writing a DWord containing status information.
The second data transfer writing a byte (SWSTYLE
cleared to ZERO) or otherwise a word containing addi-
tional status and the ownership bit (i.e. MD1[31]).
PAR
6
0110
MD0
7
PAR
8
0000
DATA
9
PAR
10
AMD
19436A-29
59