AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 143

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

3
2
1
DXCVRCTL
EADISEL
X
X
0
1
0
1
AWAKE
ASEL
Table 31. DXCVR Output Control
DXCVRPOL Network Port
0
1
0
0
1
1
Read/Write accessible always.
DXCVRPOL
H_RESET and is unaffected by
S_RESET or by setting the
STOP bit.
EADI Select. When set to ONE,
this bit enables the three EADI in-
terface pins that are multiplexed
with other functions. EESK/LED1
becomes SFBD, EEDO/LED3
becomes SRD, and LED2 be-
comes SRDCLK.
Read/Write accessible always.
EADISEL
H_RESET and is unaffected by
S_RESET or by setting the
STOP bit.
This bit selects one of two differ-
ent sleep modes.
If AWAKE is set to ONE and the
SLEEP pin is asserted, the
PCnet-PCI II controller goes into
snooze mode. If AWAKE is
cleared to ZERO and the SLEEP
pin is asserted, the PCnet-PCI II
controller goes into coma mode.
See the section “Power Saving
Modes” for more details.
This bit only has meaning when
the 10BASE-T network interface
is selected.
Read/Write accessible always.
AWAKE is cleared to ZERO by
H_RESET and is unaffected by
S_RESET or by setting the
STOP bit.
Auto Select. When set, the
PCnet-PCI II controller will auto-
matically select the operating
media interface port, unless the
user has selected GPSI mode
through appropriate program-
ming of the PORTSEL bits of the
Mode Register (CSR15). If GPSI
AUI or GPSI
AUI or GPSI
AUI or GPSI
AUI or GPSI
10BASE-T
10BASE-T
Active
is
is
cleared
cleared
DXCVR
Output
P R E L I M I N A R Y
High
High
High
Low
Low
Low
Am79C970A
by
by
0
PORTSEL[1:0] (BCR2[1])
XMAUSEL
0X
0X
00
01
10
11
Table 32. Network Port Configuration
ASEL
X
X
1
1
0
0
mode has not been selected,
ASEL has been set to ONE, and
the 10BASE-T transceiver is in
the
10BASE-T port will be used. If
GPSI mode has not been se-
lected, ASEL has been set to
ONE, and the 10BASE-T port is
in the Link Fail state, the AUI port
will be used. If one of the above
conditions changes during trans-
mission, switching between the
ports will not occur until the trans-
mission is ended.
When ASEL is set to ONE, Link
Beat Pulses will be transmitted
on the 10BASE-T port, regard-
less of the state of Link Status.
When ASEL is cleared to ZERO,
Link Beat Pulses will only be
transmitted on the 10BASE-T
port when the PORTSEL bits of
the Mode Register (CSR15)
have selected 10BASE-T as the
active port.
When ASEL is cleared to ZERO,
then the selected network port
will be determined by the settings
of the PORTSEL bits of CSR15.
Read/Write accessible always.
ASEL is set to ONE by H_RESET
and is unaffected by S_RESET
or by setting the STOP bit.
The network port configurations
are as follows:
Reserved location. Read/Write
accessible always. This reserved
location is cleared by H_RESET
and is unaffected by S_RESET
or by setting the STOP bit. Writ-
ing a ONE to this bit has no effect
on
PCnet-PCI II controller.
the
Link
(of 10BASE-T)
Link Status
Pass
Fail
operation
X
X
X
X
Pass
state,
10BASE-T
10BASE-T
AMD
Reserved
Network
GPSI
of
Port
AUI
AUI
143
the
the