AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 134

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

CSR64: Next Transmit Buffer Address Lower
Bit
31–16 RES
15–0 NXBAL
CSR65: Next Transmit Buffer Address Upper
Bit
31–16 RES
15–0 NXBAU
CSR66: Next Transmit Byte Count
Bit
31–16 RES
15–12 RES
11–0
134
AMD
NXBC
Name
Name
Name
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
next transmit buffer address from
which the PCnet-PCI II controller
will transmit an outgoing frame.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of the
next transmit buffer address from
which the PCnet-PCI II controller
will transmit an outgoing frame.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Reserved locations. Read and
written as ZEROs.
Next Transmit Byte Count. This
field is a copy of the BCNT field
of TMD1 of the next transmit
descriptor.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
accessible
accessible
accessible
P R E L I M I N A R Y
only
only
only
Am79C970A
CSR67: Next Transmit Status
Bit
31–16 RES
15–0
7–0
CSR72: Receive Descriptor Ring Counter
Bit
31–16 RES
15–0 RCVRC
CSR74: Transmit Descriptor Ring Counter
Bit
31–16 RES
15–0 XMTRC
NXST
Name
Name
Name
RES
Description
Reserved locations. Written as
ZEROs and read as undefined.
Next Transmit Status. This field
is a copy of bits 31–16 of TMD1 of
the next transmit descriptor.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Reserved locations. Read and
written as ZEROs. Accessible
only when either the STOP or the
SPND bit is set.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Receive Descriptor Ring Counter
location. Contains a two’s com-
plement binary number used to
number the current receive de-
scriptor. This counter interprets
the value in CSR76 as pointing to
the first descriptor. A counter
value of ZERO corresponds to
the last descriptor in the ring.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Transmit
Counter location. Contains a
two’s complement binary num-
ber used to number the current
Descriptor
accessible
accessible
Ring
only
only