AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 215

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

PCnet-PCI II and PCnet-PCI Differences
OVERVIEW
This appendix summarizes the enhancements of the
PCnet-PCI II controller over the PCnet-PCI controller.
The feature summary is followed by a detailed list of all
register bit changes. The document also compares the
pinout of the PCnet-PCI II controller with the pinout of
the PCnet-PCI and PCnet-SCSI (also known as Golden
Gate) to show that the Flex-I/O footprint is continued to
be supported.
NEW FEATURES
Three Volt support for PCI bus interface
Full Duplex Ethernet
272-byte Transmit FIFO, 256-byte Receive FIFO
Enhanced PCI bus transfer cycles:
— No more address stepping
— Initialization Block read in non-burst (default) or
— Added new software style and reordered the
— FIFO DMA bursts length programmable from 1
— Type of memory command for burst read trans-
— Support for fast back-to-back slave transactions
— Enhanced disconnect of I/O burst access
Allows I/O resources to be memory mapped
Eight-bit programmable PCI Latency Timer.
MIN_GNT and MAX_LAT programmable via
EEPROM
System interrupt for data parity error, master abort
or target abort in master cycles
Network activity is terminated in an orderly se-
quence after a master or target abort
Advanced parity error handling. Mode has enable
bit and status bit in RMD1 and TMD1. All network
activity is terminated in an orderly sequence. Will
only work with 32-bit software structures.
All registers in the PCI configuration space are
cleared by H_RESET
burst mode
descriptor entries to allow burst transfers for
both, descriptor read and write accesses
to indefinite
fers programmable to be either Memory Read
Line or Memory Read Multiple (controlled by
MEMCMD, BCR18, bit 9)
even when the first transaction is addressing a
different target MEMCMD, BCR18, bit 9)
APPENDIX E
Am79C970A
Expansion ROM interface supporting devices of up
to 64 K x 8. One external address latch is required.
Reading from the S_RESET port returns TRDY
right away
REQ deassertion programmable to adapt to the
requirements of some embedded systems
INTA pin programmable for pulse mode to adapt to
the requirements of some embedded systems
Some previously reserved locations in the
EEPROM map are now used for new features
Suspend mode for graceful stop and access to
the CSR without reinitialization
User Interrupt
Reduced number of transmit interrupts:
— Transmit OK disable (CSR5, bit 15). When bit
— Last Transmit Interrupt. TMD1, bit 28 is read by
Disable Transmit Stop on Underflow (CSR3, bit 6)
bit. PCnet-PCI controller recovers automatically
from transmit underflow.
Interrupt indication when coming out of sleep mode
Interrupt indication for Excessive Deferral
Address match information in Receive Descriptor
Asserting SLEEP shuts down the entire device
S_RESET (reading the RESET register) does not
affect the TMAU, except for the T-MAU in snooze
mode
LED registers programmable via EEPROM.
Magic Packet Mode
EADI interface. Multiplexed with the same LED
pins as for the PCnet-32.
GPSI interface. Multiplexed with the Expansion
ROM interface. Use of the Expansion ROM first,
then configuring the pins to the GPSI mode
is supported.
JTAG interface
Fourth LED supported
is set to ONE, a transmit interrupt is only gener-
ated on frames that suffer an error.
the PCnet-PCI II controller to determine if an
interrupt should be generated at the end of the
frame. Only interrupts for successful transmis-
sion can be suppressed. Enabled by LTINTEN
(CSR5, bit 14).
E-1