AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 154

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

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AMD
BREADE
BWRITE
DWIO
EXTREQ should not be set to
ONE when the PCnet-PCI II
controller is used in a PCI
bus application.
Read accessible always. Write
accessible only when either the
STOP or the SPND bit is set.
EXTREQ
H_RESET and or S_RESET and
is not affected by setting the
STOP bit.
Double Word I/O. When set, this
bit indicates that the PCnet-PCI II
controller is programmed for
DWord I/O (DWIO) mode. When
cleared, this bit indicates that the
PCnet-PCI II controller is pro-
grammed for Word I/O (WIO)
mode. This bit affects the I/O
Resource Offset map and it af-
fects the defined width of the
PCnet-PCI II controller’s I/O re-
sources. See the sections “Word
I/O Mode” and “Double Word I/O
Mode” for more details.
Read accessible always. DWIO
is cleared by H_RESET and is
not affected by S_RESET or by
setting the STOP bit. DWIO is
cleared by H_RESET or S_RE-
SET and is not affected by setting
the STOP bit.
Burst Read Enable. When set,
this bit enables burst mode dur-
ing memory read accesses. The
PCnet-PCI II controller can per-
form burst transfers when read-
ing the initialization block, the
descriptor ring entries (when
SWSTYLE is set to Three), and
the
cleared, this bit prevents the
device from bursting during
read accesses.
BREADE should be set to
ONE when the PCnet-PCI II
controller is used in a PC
bus application to guarantee
maximum performance.
Read accessible always. Write
accessible only when either the
STOP or the SPND bit is set.
BREADE
H_RESET and is not affected by
S_RESET or by setting the
STOP bit.
Burst Write Enable. When set,
this bit enables burst mode
during memory write accesses.
buffer
is
is
memory.
cleared
cleared
P R E L I M I N A R Y
When
Am79C970A
by
by
4–3 TSTSHDW
2–0
BCR19: EEPROM Control and Status
Bit
31–16 RES
15
PVALID
LINBC
Name
The PCnet-PCI II controller can
perform burst transfers when
writing the descriptor ring entries
(when SWSTYLE is set to Three)
and the buffer memory. When
cleared, this bit prevents the
device from bursting during
write accesses.
BWRITE should be set to
ONE when the PCnet-PCI II con-
troller
bus application to guarantee
maximum performance.
Read accessible always. Write
accessible only when either the
STOP or the SPND bit is set.
BWRITE is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
Reserved locations. Written and
read as ZEROs.
Reserved locations. Read acces-
sible always. Write accessible
only when either the STOP or the
SPND bit is set. After H_RESET,
the value in these bits will be
001b. The setting of these bits
has no effect on any PCnet-PCI II
controller function. LINBC is not
affected by S_RESET or by set-
ting the STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
EEPROM Valid status bit. A
value of ONE in this bit indicates
that a PREAD operation has oc-
curred, and that (1) there is an
EEPROM connected to the
PCnet-PCI II controller Microwire
interface pins and (2) the con-
tents read from the EEPROM
have passed the checksum veri-
fication operation. A value of
ZERO in this bit indicates that the
checksum for the entire 36 bytes
of EEPROM is incorrect or that
no EEPROM is connected to the
Microwire interface pins.
If
following an EEPROM read op-
eration
generated after H_RESET, or
requested
then all EEPROM-programma-
PVALID
is
(either
used
through
becomes
automatically
in
PREAD),
a
ZERO
PCI