AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 70

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

A typical receive poll is the product of the
following conditions:
1. PCnet-PCI II controller does not own the current
2. PCnet-PCI II controller does not own the next RDTE
If RXON is cleared to ZERO, the PCnet-PCI II controller
will never poll RDTE locations.
In order to avoid missing frames the system should have
at least on RDTE available. To minimize poll activity two
RDTEs should be available. In this case, the poll opera-
tion will only consist of the check of the status of the
current TDTE.
A typical transmit poll is the product of the following
conditions:
1. PCnet-PCI II controller does not own the current
2. PCnet-PCI II controller does not own the current
3. PCnet-PCI II controller does not own the current
Setting the TDMD bit of CSR0 will cause the microcode
controller to exit the poll counting code and immediately
perform a polling operation. If RDTE ownership has not
been previously established, then an RDTE poll will be
performed ahead of the TDTE poll. If the microcode is
not executing the poll counting code when the TDMD bit
is set, then the demanded poll of the TDTE will be
delayed until the microcode returns to the poll
counting code.
The user may change the poll time value from the de-
fault of 65,536 clock periods by modifying the value in
the Polling Interval register (CSR47).
Transmit Descriptor Table Entry
If, after a Transmit Descriptor Table Entry (TDTE) ac-
cess, the PCnet-PCI II controller finds that the OWN bit
of that TDTE is not set, the PCnet-PCI II controller re-
sumes the poll time count and re-examines the same
TDTE at the next expiration of the poll time count.
If the OWN bit of the TDTE is set, but the Start of Packet
(STP) bit is not set, the PCnet-PCI II controller will im-
mediately request the bus in order to clear the OWN bit
of this descriptor. (This condition would normally be
found following a late collision (LCOL) or retry (RTRY)
error that occurred in the middle of a transmit frame
70
DTE and the poll time has elapsed and
RXON = 1 (CSR0, bit 5), or
and there is more than one receive descriptor in the
ring
RXON = 1.
TDTE and DPOLL = 0 (CSR4, bit 12) and TXON = 1
(CSR0, bit 4) and the poll time has elapsed, or
TDTE and DPOLL = 0 and TXON = 1 and a frame
has just been received, or
TDTE and DPOLL = 0 and TXON = 1 and a frame
has just been transmitted.
AMD
and
the
poll
time
has
elapsed
P R E L I M I N A R Y
Am79C970A
and
chain of buffers.) After resetting the OWN bit of this de-
scriptor, the PCnet-PCI II controller will again
immediately request the bus in order to access the next
TDTE location in the ring.
If the OWN bit is set and the buffer length is 0, the OWN
bit will be cleared. In the C-LANCE the buffer length of 0
is interpreted as a 4096-byte buffer. A zero length buff-
ers is acceptable as long as it is not the last buffer in a
chain (STP = 0 and ENP = 1).
If the OWN bit and STP are set, then microcode control
proceeds to a routine that will enable transmit data
transfers to the FIFO. The PCnet-PCI II controller will
look ahead to the next transmit descriptor after it has
performed at least one transmit data transfer from the
first buffer.
If the PCnet-PCI II controller does not own the next
TDTE (i.e. the second TDTE for this frame), it will com-
plete transmission of the current buffer and update the
status of the current (first) TDTE with the BUFF and
UFLO bits being set. If DXSUFLO (CSR3, bit 6) is
cleared to ZERO, the underflow error will cause the
transmitter to be disabled (CSR0, TXON = 0). The
PCnet-PCI II controller will have to be re-initialized to re-
store the transmit function. Setting DXSUFLO to ONE
enables the PCnet-PCI II controller to gracefully recover
from an underflow error. The device will scan the trans-
mit descriptor ring until it finds either the start of a new
frame or a TDTE it does not own. To avoid an underflow
situation in a chained buffer transmission, the system
should always set the transmit chain descriptor own bits
in reverse order.
If the PCnet-PCI II controller does own the second
TDTE in a chain, it will gradually empty the contents of
the first buffer (as the bytes are needed by the transmit
operation), perform a single-cycle DMA transfer to up-
date the status of the first descriptor (clear the OWN bit
in TMD1), and then it may perform one data DMA ac-
cess on the second buffer in the chain before executing
another lookahead operation. (i.e. a lookahead to the
third descriptor.)
It is imperative that the host system never reads the
TDTE OWN bits out of order. The PCnet-PCI II control-
ler normally clears OWN bits in strict FIFO order. How-
ever, the PCnet-PCI II controller can queue up to two
frames in the transmit FIFO. When the second frame
uses buffer chaining, the PCnet-PCI II controller might
return ownership out of normal FIFO order. The OWN
bit for last (and maybe only) buffer of the first frame is not
cleared until transmission is completed. During the
transmission the PCnet-PCI II controller will read in buff-
ers for the next frame and clear their OWN bits for all but
the last one. The first and all intermediate buffers of the
second frame can have their OWN bits cleared before