AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 62

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

FIFO DMA Transfers
PCnet-PCI II controller microcode will determine when a
FIFO DMA transfer is required. This transfer mode will
be used for transfers of data to and from the
PCnet-PCI II controller FIFOs. Once the PCnet-PCI II
controller BIU has been granted bus mastership, it will
perform a series of consecutive transfer cycles before
relinquishing the bus. All transfers within the master cy-
cle will be either read or write cycles, and all transfers
will be to contiguous, ascending addresses. Both non-
burst and burst cycles are used, with burst mode being
the preferred mode when the device is used in a PCI
bus application.
Non-Burst FIFO DMA Transfers
In the default mode the PCnet-PCI II controller uses
non-burst transfers to read and write data when
accessing the FIFOs. Each non-burst transfer will be
performed sequentially, with the issue of an address,
and the transfer of the corresponding data with appropri-
ate output signals to indicate selection of the active data
bytes during the transfer. FRAME will be deasserted
62
AMD
DEVSEL
FRAME
TRDY
IRDY
C/BE
REQ
GNT
PAR
CLK
AD
Figure 29. Descriptor Ring Write In Burst Mode
1
DEVSEL is sampled
2
0110
MD2
P R E L I M I N A R Y
3
Am79C970A
PAR
4
0000
after every address phase. The number of data transfer
cycles contained within a single bus mastership period
is in general dependent on the programming of the
DMAPLUS option (CSR4, bit 14). Several other factors
will also affect the length of the bus mastership period.
The possibilities are as follows:
If DMAPLUS is cleared to ZERO, a maximum of 16
transfers will be performed by default. This default value
may be changed by writing to the DMA Transfer Counter
(CSR80). Note that DMAPLUS = 0 merely sets a
maximum value. The minimum number of transfers in
the bus mastership period will be determined by all of
the following variables: the settings of the FIFO water-
marks (CSR80), the conditions of the FIFOs, the value
of the DMA Transfer Counter (CSR80), the value of the
DMA Bus Timer (CSR82), and any occurrence of
preemption
mastership period.
If DMAPLUS is set to ONE, bus cycles will continue until
the transmit FIFO is filled to its high threshold (read
transfers) or the receive FIFO is emptied to its low
DATA
5
PAR
6
that
0011
DATA
takes
7
PAR
place
8
during
19436A-32
the
bus