mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 70

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

1
Port Integration Module (S12VRPIMV2)
2.3.20
70
Address 0x024C
Read: Anytime
Write: Anytime
DDRS
DDRS
PERS
Field
Field
Reset
5-0
1
0
W
R
Data Direction Register port S —
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SCI the I/O state will be forced to be input or output. The enabled
routed LINPHY forces the I/O state to be an output (LPDR[LPDR1]). In these cases the data direction bit will not
change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Data Direction Register port S —
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SCI the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
Pull device Enable Register port S — Enable pull device on input pin or wired-or output pin
This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
only effect if used in wired-or mode. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
Port S Pull Device Enable Register (PERS)
0
0
7
Table 2-19. DDRS Register Field Descriptions (continued)
Figure 2-18. Port S Pull Device Enable Register (PERS)
0
0
6
Table 2-20. PERS Register Field Descriptions
MC9S12VR Family Reference Manual,
Preliminary - Subject to Change Without Notice
PERS5
5
1
PERS4
1
4
Description
Description
PERS3
1
3
Rev. 2.2
PERS2
1
2
Freescale Semiconductor
PERS1
Access: User read/write
1
1
PERS0
0
1
1