mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 270

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mc9s12vr48

Manufacturer Part Number
mc9s12vr48
Description
S12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Analog-to-Digital Converter (ADC12B6CV2)
8.3.2.10
Read: Anytime
Write: Anytime
8.3.2.11
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
270
Module Base + 0x000C
Module Base + 0x000E
CMPHT[5:0]
IEN[5:0]
Reset
Reset
Field
Field
5–0
5–0
W
W
R
R
15
15
1
1
0
0
ATD Digital Input Enable on channel x (x= 5, 4, 3, 2, 1, 0) — This bit controls the digital input buffer from the
analog input pin (ANx) to the digital data register.
0 Disable digital input buffer to ANx pin
1 Enable digital input buffer on ANx pin.
Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while
ATD Input Enable Register (ATDDIEN)
ATD Compare Higher Than Register (ATDCMPHT)
Compare Operation Higher Than Enable for conversion number n (n= 5, 4, 3, 2, 1, 0) of a Sequence (n
conversion number, NOT channel number!) — This bit selects the operator for comparison of conversion
results.
0 If result of conversion n is lower or same than compare value in ATDDRn, this is flagged in ATDSTAT2
1 If result of conversion n is higher than compare value in ATDDRn, this is flagged in ATDSTAT2
= Unimplemented or Reserved
= Unimplemented or Reserved
14
14
1
1
0
0
simultaneously using it as an analog port, there is potentially increased power consumption because the
digital input buffer maybe in the linear region.
Figure 8-13. ATD Compare Higher Than Register (ATDCMPHT)
13
13
1
1
0
0
Figure 8-12. ATD Input Enable Register (ATDDIEN)
12
12
1
1
0
0
Table 8-20. ATDCMPHT Field Descriptions
MC9S12VR Family Reference Manual,
Preliminary - Subject to Change Without Notice
Table 8-19. ATDDIEN Field Descriptions
11
11
1
1
0
0
10
10
1
1
0
0
9
1
1
9
0
0
1
1
0
0
8
8
Description
Description
1
1
0
0
7
7
1
1
0
0
6
6
Rev. 2.2
5
0
5
0
0
0
4
4
CMPHT[5:0]
0
0
3
IEN[5:0]
3
Freescale Semiconductor
0
0
2
2
0
0
1
1
0
0
0
0

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