mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 390

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Timer Module (TIM16B8CV3)
For the description of PACLK please refer
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an
input clock to the timer counter. The change from one selected clock to the other happens immediately
after these bits are written.
12.3.2.16 Pulse Accumulator Flag Register (PAFLG)
1
Read: Anytime
Write: Anytime
390
Module Base + 0x0021
This register is available only when channel 7 exists and is reserved if that channel does not exist. Writes to a reserved register
have no functional effect. Reads from a reserved register return zeroes.
Reset
W
R
0
0
7
If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64
because the ÷64 clock is generated by the timer prescaler.
PAMOD
CLK1
Unimplemented or Reserved
0
0
1
1
0
0
1
1
Figure 12-25. Pulse Accumulator Flag Register (PAFLG)
0
0
6
PEDGE
CLK0
MC9S12VR Family Reference Manual,
Preliminary - Subject to Change Without Notice
0
1
0
1
0
1
0
1
Table 12-20. Timer Clock Selection
0
0
5
Table 12-19. Pin Action
Use PACLK/65536 as timer counter clock frequency
Use PACLK/256 as timer counter clock frequency
Figure
Use timer prescaler clock as timer counter clock
Div. by 64 clock enabled with pin high level
Use PACLK as input to timer counter clock
Div. by 64 clock enabled with pin low level
NOTE
12-30.
0
0
4
Timer Clock
Falling edge
Rising edge
Pin Action
0
0
3
Rev. 2.2
0
0
2
PAOVF
Freescale Semiconductor
0
1
PAIF
0
0