mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 282

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mc9s12vr48

Manufacturer Part Number
mc9s12vr48
Description
S12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Pulse-Width Modulator (S12PWM8B8CV2)
1
2
9.3.2.1
Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx
bits are set (PWMEx = 1), the associated PWM output is enabled immediately. However, the actual PWM
waveform is not available on the associated PWM output until its clock source begins its next cycle due to
the synchronization of PWMEx and the clock source.
An exception to this is when channels are concatenated. Once concatenated mode is enabled (CONxx bits
set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the
low order PWMEx bit. In this case, the high order bytes PWMEx bits have no effect and their
corresponding PWM output lines are disabled.
While in run mode, if all existing PWM channels are disabled (PWMEx–0 = 0), the prescaler counter shuts
off for power savings.
Read: Anytime
Write: Anytime
282
Module Base + 0x0000
RESERVED
RESERVED
RESERVED
The related bit is available only if corresponding channel exists.
The register is available only if corresponding channel exists.
Register
0x0025
0x0026
0x0027
Reset
Name
W
R
PWME7
W
W
W
R
R
R
PWM Enable Register (PWME)
0
7
The first PWM cycle after enabling the channel can be irregular.
Bit 7
0
0
0
Figure 9-2. The scalable PWM Register Summary (Sheet 4 of 4)
PWME6
0
6
= Unimplemented or Reserved
6
0
0
0
Figure 9-3. PWM Enable Register (PWME)
MC9S12VR Family Reference Manual,
Preliminary - Subject to Change Without Notice
PWME5
0
5
5
0
0
0
PWME4
NOTE
0
4
4
0
0
0
PWME3
0
3
3
0
0
0
Rev. 2.2
PWME2
0
2
2
0
0
0
PWME1
Freescale Semiconductor
0
1
1
0
0
0
PWME0
Bit 0
0
0
0
0
0

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