mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 170

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Clock, Reset and Power Management (S12CPMU_UHV)
S12CPMU_UHV generates a Clock Monitor Reset. In Full Stop Mode the external oscillator and the clock
monitor are disabled.
4.5.2.2
The COP (free running watchdog timer) enables the user to check that a program is running and
sequencing properly. When the COP is being used, software is responsible for keeping the COP from
timing out. If the COP times out it is an indication that the software is no longer being executed in the
intended sequence; thus COP reset is generated.
The clock source for the COP is either ACLK, IRCCLK or OSCCLK depending on the setting of the
COPOSCSEL0 and COPOSCSEL1 bit.
Due to clock domain crossing synchronization there is a latency time to enter and exit Stop Mode if the
COP clock source is ACLK and this clock is stopped in Stop Mode. This maximum total latency time is 4
ACLK cycles (2 ACLK cycles for Stop Mode entry and exit each) which must be added to the Stop Mode
recovery time t
occurs no matter which Stop Mode (Full, Pseudo) is currently exited or entered next.
After exit from Stop Mode (Pseudo, Full) for this latency time of 2 ACLK cycles no Stop Mode request
(STOP instruction) should be generated to make sure the COP counter can increment at each Stop Mode
exit.
Table 4-31
configuration and status bit settings:
170
COPOSCSEL1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
gives an overview of the COP condition (run, static) in Stop Mode depending on legal
Computer Operating Properly Watchdog (COP) Reset
STP_REC
CSAD
0
1
x
x
x
x
x
x
x
x
x
x
x
x
PSTP
x
x
1
1
1
1
1
0
0
0
0
0
0
0
from exit of current Stop Mode to entry of next Stop Mode. This latency time
Table 4-31. COP condition (run, static) in Stop Mode
PCE
x
x
1
1
1
0
0
1
1
1
0
0
0
0
MC9S12VR Family Reference Manual,
Preliminary - Subject to Change Without Notice
COPOSCSEL0
x
x
1
0
0
0
1
1
0
0
1
0
0
0
OSCE
x
x
1
0
1
x
1
1
1
0
1
1
1
0
UPOSC
x
x
1
x
x
x
1
1
x
0
1
1
0
0
Rev. 2.2
COP counter behavior in Stop Mode
Static (OSCCLK)
Static (OSCCLK)
Satic (OSCCLK)
Static (IRCCLK)
Static (IRCCLK)
Static (IRCCLK)
Static (IRCCLK)
Static (IRCCLK)
Static (IRCCLK)
Static (IRCCLK)
Static (IRCCLK)
Run (OSCCLK)
(clock source)
Static (ACLK)
Freescale Semiconductor
Run (ACLK)