mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 346

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Serial Peripheral Interface (S12SPIV5)
For a detailed description of operating modes, please refer to
11.1.4
Figure 11-1
data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic.
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Run mode
This is the basic mode of operation.
Wait mode
SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit
located in the SPICR2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in
run mode. If the SPISWAI bit is set, the SPI goes into a power conservative state, with the SPI clock
generation turned off. If the SPI is configured as a master, any transmission in progress stops, but
is resumed after CPU goes into run mode. If the SPI is configured as a slave, reception and
transmission of data continues, so that the slave stays synchronized to the master.
Stop mode
The SPI is inactive in stop mode for reduced power consumption. If the SPI is configured as a
master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI
is configured as a slave, reception and transmission of data continues, so that the slave stays
synchronized to the master.
Block Diagram
gives an overview on the SPI architecture. The main parts of the SPI are status, control and
MC9S12VR Family Reference Manual,
Preliminary - Subject to Change Without Notice
Section 11.4.7, “Low Power Mode
Rev. 2.2
Freescale Semiconductor
Options”.