mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 236

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

S12S Debug Module (S12SDBGV2)
6.5
6.5.1
Defining the state control registers as SCR1,SCR2, SCR3 and M0,M1,M2 as matches on channels 0,1,2
respectively. SCR encoding supported by S12SDBGV1 are shown in black. SCR encoding supported only
in S12SDBGV2 are shown in red. For backwards compatibility the new scenarios use a 4th bit in each SCR
register. Thus the existing encoding for SCRx[2:0] is not changed.
6.5.2
A trigger is generated if a given sequence of 3 code events is executed.
Scenario 1 is possible with S12SDBGV1 SCR encoding
6.5.3
A trigger is generated if a given sequence of 2 code events is executed.
236
SCR1=0011
SCR1=0011
State1
State1
Application Information
State Machine scenarios
Scenario 1
Scenario 2
When program control returns from a tagged breakpoint using an RTI or
BDM GO command without program counter modification it returns to the
instruction whose tag generated the breakpoint. To avoid a repeated
breakpoint at the same location reconfigure the DBG module in the SWI
routine, if configured for an SWI breakpoint, or over the BDM interface by
executing a TRACE command before the GO to increment the program flow
past the tagged instruction.
M1
M1
SCR2=0010
SCR2=0101
MC9S12VR Family Reference Manual,
State2
State2
Preliminary - Subject to Change Without Notice
Figure 6-28. Scenario 2a
Figure 6-27. Scenario 1
M2
M2
NOTE
Final State
SCR3=0111
State3
Rev. 2.2
M0
Final State
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