mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 138

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mc9s12vr48

Manufacturer Part Number
mc9s12vr48
Description
S12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Clock, Reset and Power Management (S12CPMU_UHV)
4.3.2.8
This register selects the time-out period for the Real Time Interrupt.
The clock source for the RTI is either IRCCLK or OSCCLK depending on the setting of the RTIOSCSEL
bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode) and RTIOSCSEL=1 the RTI continues to run, else
the RTI counter halts in Stop Mode.
Read: Anytime
Write: Anytime
138
0x003B
RTR[6:4]
RTR[3:0]
RTDEC
Reset
Field
6–4
3–0
7
W
R
RTDEC
Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values.
0 Binary based divider value. See
1 Decimal based divider value. See
Real Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI.See
and
Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to
provide additional
CPMURTI register.
S12CPMU_UHV RTI Control Register (CPMURTI)
0
7
A write to this register starts the RTI time-out period. A change of the
RTIOSCSEL bit (writing a different value or loosing UPOSC status)
re-starts the RTI time-out period.
Table
4-11.
Figure 4-11. S12CPMU_UHV RTI Control Register (CPMURTI)
RTR6
0
6
granularity.Table 4-10
MC9S12VR Family Reference Manual,
Preliminary - Subject to Change Without Notice
Table 4-9. CPMURTI Field Descriptions
RTR5
0
5
Table 4-10
Table 4-11
and
RTR4
NOTE
Table 4-11
0
4
Description
show all possible divide values selectable by the
RTR3
0
3
Rev. 2.2
RTR2
0
2
Freescale Semiconductor
RTR1
0
1
Table 4-10
RTR0
0
0

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