mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 186

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Background Debug Module (S12SBDMV1)
For hardware data read commands, the external host must wait at least 150 bus clock cycles after sending
the address before attempting to obtain the read data. This is to be certain that valid data is available in the
BDM shift register, ready to be shifted out. For hardware write commands, the external host must wait
150 bus clock cycles after sending the data to be written before attempting to send a new command. This
is to avoid disturbing the BDM shift register before the write has been completed. The 150 bus clock cycle
delay in both cases includes the maximum 128 cycle delay that can be incurred as the BDM waits for a
free cycle before stealing a cycle.
For BDM firmware read commands, the external host should wait at least 48 bus clock cycles after sending
the command opcode and before attempting to obtain the read data. The 48 cycle wait allows enough time
for the requested data to be made available in the BDM shift register, ready to be shifted out.
For BDM firmware write commands, the external host must wait 36 bus clock cycles after sending the data
to be written before attempting to send a new command. This is to avoid disturbing the BDM shift register
before the write has been completed.
The external host should wait for at least for 76 bus clock cycles after a TRACE1 or GO command before
starting any new serial command. This is to allow the CPU to exit gracefully from the standard BDM
firmware lookup table and resume execution of the user code. Disturbing the BDM shift register
prematurely may adversely affect the exit from the standard BDM firmware lookup table.
Figure 5-6
times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles
in the high state. The time for an 8-bit command is 8 × 16 target clock cycles.
1. Target clock cycles are cycles measured using the target MCU’s serial clock rate. See
186
and
Section 5.3.2.1, “BDM Status Register (BDMSTS)”
represents the BDM command structure. The command blocks illustrate a series of eight bit
16-bit misaligned reads and writes are generally not allowed. If attempted
by BDM hardware command, the BDM ignores the least significant bit of
the address and assumes an even address from the remaining bits.
If the bus rate of the target processor is unknown or could be changing, it is
recommended that the ACK (acknowledge function) is used to indicate
when an operation is complete. When using ACK, the delay times are
automated.
MC9S12VR Family Reference Manual,
Preliminary - Subject to Change Without Notice
for information on how serial clock rate is selected.
NOTE
Rev. 2.2
Section 5.4.6, “BDM Serial Interface”
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