mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 243

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 7
Interrupt Module (S12SINTV1)
7.1
The INT module decodes the priority of all system exception requests and provides the applicable vector
for processing the exception to the CPU. The INT module supports:
Each of the I bit maskable interrupt requests is assigned to a fixed priority level.
7.1.1
Table 7-2
7.1.2
Freescale Semiconductor
Number
Version
01.02
01.03
01.04
•
•
•
•
•
•
•
I bit and X bit maskable interrupt requests
A non-maskable unimplemented op-code trap
A non-maskable software interrupt (SWI) or background debug mode request
Three system reset vector requests
A spurious interrupt vector
Interrupt vector base register (IVBR)
One spurious interrupt vector (at address vector base
Introduction
contains terms and abbreviations used in the document.
Revision
20 May
13 Sep
21 Nov
Glossary
Features
Date
2007
2007
2009
Effective
Date
Term
MCU
MC9S12VR Family Reference Manual, Rev. 2.2
CCR
ISR
Preliminary - Subject to Change Without Notice
Author
Table 7-2. Terminology
Condition Code Register (in the CPU)
Interrupt Service Routine
Micro-Controller Unit
updates for S12P family devices:
- re-added XIRQ and IRQ references since this functionality is used
on devices without D2D
- added low voltage reset as possible source to the pin reset vector
added clarification of “Wake-up from STOP or WAIT by XIRQ with
X bit set” feature
added footnote about availability of “Wake-up from STOP or WAIT
by XIRQ with X bit set” feature
Meaning
1
+ 0x0080).
Description of Changes
243