mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 354

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mc9s12vr48

Manufacturer Part Number
mc9s12vr48
Description
S12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Serial Peripheral Interface (S12SPIV5)
11.3.2.4
Read: Anytime
Write: Has no effect
354
Module Base +0x0003
SPPR2
Reset
Field
SPIF
1
1
1
1
1
1
1
1
1
1
1
1
1
7
W
R
SPIF
SPIF Interrupt Flag — This bit is set after received data has been transferred into the SPI data register. For
information about clearing SPIF Flag, please refer to
0 Transfer not yet complete.
1 New data copied to SPIDR.
Table 11-7. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 3 of 3)
SPI Status Register (SPISR)
0
7
SPPR1
1
1
1
1
1
1
1
1
1
1
1
1
1
= Unimplemented or Reserved
0
0
6
SPPR0
0
0
0
0
0
1
1
1
1
1
1
1
1
MC9S12VR Family Reference Manual,
Figure 11-6. SPI Status Register (SPISR)
Preliminary - Subject to Change Without Notice
Table 11-8. SPISR Field Descriptions
SPTEF
1
5
SPR2
0
1
1
1
1
0
0
0
0
1
1
1
1
MODF
SPR1
0
4
1
0
0
1
1
0
0
1
1
0
0
1
1
Description
Table
SPR0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
11-9.
3
Rev. 2.2
Baud Rate
Divisor
1792
1024
2048
0
0
2
112
224
448
896
128
256
512
16
32
64
Freescale Semiconductor
0
0
1
1.5625 Mbit/s
223.21 kbit/s
111.61 kbit/s
781.25 kbit/s
390.63 kbit/s
195.31 kbit/s
55.80 kbit/s
27.90 kbit/s
13.95 kbit/s
97.66 kbit/s
48.83 kbit/s
24.41 kbit/s
12.21 kbit/s
Baud Rate
0
0
0

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