mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 387

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

12.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime
Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero
will not affect current status of the bit.
Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
12.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit
to one while TEN bit of TSCR1 or PAEN bit of PACTL is set to one.
Read: Anytime
Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared).
Freescale Semiconductor
Module Base + 0x000E
Module Base + 0x000F
C[7:0]F
Reset
Reset
Field
7:0
unavailable bits return a zero.
W
W
R
R
Input Capture/Output Compare Channel “x” Flag — These flags are set when an input capture or output
compare event occurs. Clearing requires writing a one to the corresponding flag bit while TEN or PAEN is set to
one.
Note: When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare
TOF
C7F
0
0
7
7
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
channel (0x0010–0x001F) will cause the corresponding channel flag CxF to be cleared.
Unimplemented or Reserved
C6F
0
0
0
6
6
Figure 12-20. Main Timer Interrupt Flag 1 (TFLG1)
Figure 12-21. Main Timer Interrupt Flag 2 (TFLG2)
MC9S12VR Family Reference Manual, Rev. 2.2
Preliminary - Subject to Change Without Notice
Table 12-16. TRLG1 Field Descriptions
C5F
0
0
0
5
5
C4F
NOTE
0
0
0
4
4
Description
C3F
0
0
0
3
3
C2F
0
0
0
2
2
Timer Module (TIM16B8CV3)
C1F
0
0
0
1
1
C0F
0
0
0
0
0
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