mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 301

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

9.4.2.6
For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the
corresponding PWM output will be center aligned.
The 8-bit counter operates as an up/down counter in this mode and is set to up whenever the counter is
equal to $00. The counter compares to two registers, a duty register and a period register as shown in the
block diagram in
changes state, causing the PWM waveform to also change state. A match between the PWM counter and
the period register changes the counter direction from an up-count to a down-count. When the PWM
counter decrements and matches the duty register again, the output flip-flop changes state causing the
PWM output to also change state. When the PWM counter decrements and reaches zero, the counter
direction changes from a down-count back to an up-count and a load from the double buffer period and
duty registers to the associated registers is performed, as described in
Duty”. The counter counts from 0 up to the value in the period register and then back down to 0. Thus the
effective period is PWMPERx*2.
To calculate the output frequency in center aligned output mode for a particular channel, take the selected
clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period
register for that channel.
As an example of a center aligned output, consider the following case:
Freescale Semiconductor
•
•
PWMx Frequency = Clock (A, B, SA, or SB) / (2*PWMPERx)
PWMx Duty Cycle (high time as a% of period):
— Polarity = 0 (PPOLx = 0)
— Polarity = 1 (PPOLx = 1)
PPOLx = 0
PPOLx = 1
Center Aligned Outputs
Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%
Duty Cycle = [PWMDTYx / PWMPERx] * 100%
Changing the PWM output mode from left aligned to center aligned output
(or vice versa) while channels are operating can cause irregularities in the
PWM output. It is recommended to program the output mode before
enabling the PWM channel.
Figure
9-16. When the PWM counter matches the duty register, the output flip-flop
Figure 9-19. PWM Center Aligned Output Waveform
PWMDTYx
MC9S12VR Family Reference Manual, Rev. 2.2
Preliminary - Subject to Change Without Notice
PWMPERx
Period = PWMPERx*2
NOTE
PWMPERx
Section 9.4.2.3, “PWM Period and
Pulse-Width Modulator (S12PWM8B8CV2)
PWMDTYx
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