mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 201

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

6.1.4
The DBG module can be used in all MCU functional modes.
During BDM hardware accesses and whilst the BDM module is active, CPU monitoring is disabled. When
the CPU enters active BDM Mode through a BACKGROUND command, the DBG module, if already
armed, remains armed.
The DBG module tracing is disabled if the MCU is secure, however, breakpoints can still be generated
6.1.5
Freescale Semiconductor
Enable
BDM
•
x
0
0
1
1
TAGHITS
SECURE
CPU BUS
4-stage state sequencer for trace buffer control
— Tracing session trigger linked to Final State of state sequencer
— Begin and End alignment of tracing to trigger
READ TRACE DATA (DBG READ DATA BUS)
Modes of Operation
Block Diagram
Active
BDM
0
1
0
1
x
Secure
MCU
1
0
0
0
0
Table 6-2. Mode Dependent Restriction Summary
COMPARATOR A
COMPARATOR C
COMPARATOR B
MC9S12VR Family Reference Manual, Rev. 2.2
Figure 6-1. Debug Module Block Diagram
Preliminary - Subject to Change Without Notice
Matches Enabled
Comparator
Yes
Yes
Yes
No
MATCH1
MATCH2
MATCH0
Active BDM not possible when not enabled
Breakpoints
Only SWI
Possible
Yes
Yes
No
CONTROL
MATCH
LOGIC
TAG &
TRANSITION
STATE
BREAKPOINT REQUESTS
Possible
Tagging
S12S Debug Module (S12SDBGV2)
Yes
Yes
Yes
No
TO CPU
TRACE BUFFER
TAGS
STATE SEQUENCER
STATE
TRACE
CONTROL
TRIGGER
Possible
Tracing
Yes
Yes
No
No
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