mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 237

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

A trigger is generated if a given sequence of 2 code events is executed, whereby the first event is entry into
a range (COMPA,COMPB configured for range mode). M1 is disabled in range modes.
A trigger is generated if a given sequence of 2 code events is executed, whereby the second event is entry
into a range (COMPA,COMPB configured for range mode)
All 3 scenarios 2a,2b,2c are possible with the S12SDBGV1 SCR encoding
6.5.4
A trigger is generated immediately when one of up to 3 given events occurs
Scenario 3 is possible with S12SDBGV1 SCR encoding
6.5.5
Trigger if a sequence of 2 events is carried out in an incorrect order. Event A must be followed by event B
and event B must be followed by event A. 2 consecutive occurrences of event A without an intermediate
Freescale Semiconductor
SCR1=0111
SCR1=0010
State1
State1
Scenario 3
Scenario 4
M01
M2
SCR1=0000
SCR2=0101
SCR2=0011
State1
MC9S12VR Family Reference Manual, Rev. 2.2
State2
State2
Preliminary - Subject to Change Without Notice
Figure 6-29. Scenario 2b
Figure 6-30. Scenario 2c
Figure 6-31. Scenario 3
M012
M2
M0
Final State
Final State
Final State
S12S Debug Module (S12SDBGV2)
237