mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 175

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 5
Background Debug Module (S12SBDMV1)
5.1
This section describes the functionality of the background debug module (BDM) sub-block of the HCS12S
core platform.
The background debug module (BDM) sub-block is a single-wire, background debug system implemented
in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD
pin.
The BDM has enhanced capability for maintaining synchronization between the target and host while
allowing more flexibility in clock rates. This includes a sync signal to determine the communication rate
and a handshake signal to indicate when an operation is complete. The system is backwards compatible to
the BDM of the S12 family with the following exceptions:
5.1.1
The BDM includes these distinctive features:
Freescale Semiconductor
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Revision Number
TAGGO command not supported by S12SBDM
External instruction tagging feature is part of the DBG module
S12SBDM register map and register content modified
Family ID readable from BDM ROM at global address 0x3_FF0F in active BDM
(value for devices with HCS12S core is 0xC2)
Clock switch removed from BDM (CLKSW bit removed from BDMSTS register)
Single-wire communication with host development system
Enhanced capability for allowing more flexibility in clock rates
SYNC command to determine communication rate
GO_UNTIL command
Hardware handshake protocol to increase the performance of the serial communication
Introduction
1.03
1.04
1.05
Features
14.May.2009
07.Dec.2010
30.Nov.2009
Date
MC9S12VR Family Reference Manual, Rev. 2.2
Preliminary - Subject to Change Without Notice
Table 5-1. Revision History
Internal Conditional text only
Internal Conditional text only
Standardized format of revision history table header.
Summary of Changes
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