mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 159

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

4.3.2.21
This registers configures the external oscillator (XOSCLCP).
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has
no effect.
Freescale Semiconductor
0x02FA
Reserved
Reserved
Reset
OSCE
Field
4-0
7
6
W
R
OSCE
Oscillator Enable Bit — This bit enables the external oscillator (XOSCLCP). The UPOSC status bit in the
CPMUFLG register indicates when the oscillation is stable and OSCCLK can be selected as Bus Clock or source
of the COP or RTI.A loss of oscillation will lead to a clock monitor reset.This
0 External oscillator is disabled.
1 External oscillator is enabled. Clock monitor is enabled. External oscillator is qualified by PLLCLK
Note: When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop
Do not alter this bit from its reset value.It is for Manufacturer use only and can change the PLL behavior.
Do not alter these bits from their reset value. These are for Manufacturer use only and can change the PLL
S12CPMU_UHV Oscillator Register (CPMUOSC)
0
7
REFCLK for PLL is IRCCLK.
REFCLK for PLL is the external oscillator clock divided by REFDIV.
behavior.
Be aware that the output frequency varies with the TC trimming. A
frequency trimming correction is therefore necessary. The values provided
in
device to device.
Write to this register clears the LOCK and UPOSC status bits.
Table 4-26
Mode with OSCE bit already 1) the software must wait for a minimum time equivalent to the startup-time
of the external oscillator t
Reserved
Figure 4-30. S12CPMU_UHV Oscillator Register (CPMUOSC)
0
6
are typical values at ambient temperature which can vary from
MC9S12VR Family Reference Manual, Rev. 2.2
Table 4-27. CPMUOSC Field Descriptions
Preliminary - Subject to Change Without Notice
0
0
5
UPOSC
before entering Pseudo Stop Mode.
NOTE.
0
4
Description
Clock, Reset and Power Management (S12CPMU_UHV)
0
3
Reserved
0
2
0
1
0
0
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