mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 230

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

S12S Debug Module (S12SDBGV2)
6.4.5.3
ADRH, ADRM, ADRL denote address high, middle and low byte respectively. The numerical suffix refers
to the tracing count. The information format for Loop1 and Normal modes is identical. In Detail mode, the
address and data for each entry are stored on consecutive lines, thus the maximum number of entries is 32.
In this case DBGCNT bits are incremented twice, once for the address line and once for the data line, on
each trace buffer entry. In Detail mode CINF comprises of R/W and size access information (CRW and
CSZ respectively).
Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer (DATAL)
and the high byte is cleared. When tracing word accesses, the byte at the lower address is always stored to
trace buffer byte1 and the byte at the higher address is stored to byte0.
6.4.5.3.1
The format of the bits is dependent upon the active trace mode as described below.
Field2 Bits in Detail Mode
In Detail Mode the CSZ and CRW bits indicate the type of access being made by the CPU.
230
Normal/Loop1
Detail Mode
Modes
Mode
Trace Buffer Organization (Normal, Loop1, Detail modes)
When tracing is terminated using forced breakpoints, latency in breakpoint
generation means that opcodes following the opcode causing the breakpoint
can be stored to the trace buffer. The number of opcodes is dependent on
program flow. This can be avoided by using tagged breakpoints.
Information Bit Organization
Number
Entry 1
Entry 2
Entry 1
Entry 2
Entry
Table 6-37. Trace Buffer Organization (Normal,Loop1,Detail modes)
CINF1,ADRH1
CINF2,ADRH2
Field 2
4-bits
PCH1
PCH2
MC9S12VR Family Reference Manual,
Preliminary - Subject to Change Without Notice
0
0
Figure 6-25. Field2 Bits in Detail Mode
Bit 3
CSZ
CRW
Bit 2
NOTE:
DATAH1
DATAH2
ADRM1
ADRM2
ADDR[17] ADDR[16]
Field 1
PCM1
PCM2
8-bits
Bit 1
Bit 0
Rev. 2.2
DATAL1
DATAL2
Field 0
ADRL1
ADRL2
8-bits
PCL1
PCL2
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