mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 389

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

12.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL)
1
Read: Any time
Write: Any time
When PAEN is set, the Pulse Accumulator counter is enabled.The Pulse Accumulator counter shares the
input pin with IOC7.
Freescale Semiconductor
Module Base + 0x0020
This register is available only when channel 7 exists and is reserved if that channel does not exist. Writes to a reserved register
have no functional effect. Reads from a reserved register return zeroes.
CLK[1:0]
PAMOD
PEDGE
Reset
PAOVI
PAEN
Field
PAI
3:2
6
5
4
1
0
W
R
Pulse Accumulator System Enable — PAEN is independent from TEN. With timer disabled, the pulse
accumulator can function unless pulse accumulator is disabled.
0 16-Bit Pulse Accumulator system disabled.
1 Pulse Accumulator system enabled.
Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1). See
Table
0 Event counter mode.
1 Gated time accumulation mode.
Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1).
For PAMOD bit = 0 (event counter mode). See
0 Falling edges on IOC7 pin cause the count to be increased.
1 Rising edges on IOC7 pin cause the count to be increased.
For PAMOD bit = 1 (gated time accumulation mode).
0 IOC7 input pin high enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing falling
1 IOC7 input pin low enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing rising edge
Clock Select Bits — Refer to
Pulse Accumulator Overflow Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAOVF is set.
Pulse Accumulator Input Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAIF is set.
0
0
7
edge on IOC7 sets the PAIF flag.
on IOC7 sets the PAIF flag.
12-19.
Figure 12-24. 16-Bit Pulse Accumulator Control Register (PACTL)
Unimplemented or Reserved
PAEN
0
6
MC9S12VR Family Reference Manual, Rev. 2.2
Preliminary - Subject to Change Without Notice
Table 12-18. PACTL Field Descriptions
PAMOD
Table
0
5
12-20.
PEDGE
0
4
Table
Description
12-19.
CLK1
0
3
CLK0
0
2
Timer Module (TIM16B8CV3)
PAOVI
0
1
PAI
0
0
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