mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 257

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mc9s12vr48

Manufacturer Part Number
mc9s12vr48
Description
S12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
8.3.2
This section describes in address order all the ADC12B6C registers and their individual bits.
8.3.2.1
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime, in special modes always write 0 to Reserved Bit 7.
Freescale Semiconductor
Module Base + 0x0000
WRAP[3-0]
Reset
Field
3-0
W
R
Reserved
Register Descriptions
Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing
multi-channel conversions. The coding is summarized in
ATD Control Register 0 (ATDCTL0)
0
7
WRAP3 WRAP2 WRAP1 WRAP0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
= Unimplemented or Reserved
0
0
6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Table 8-2. Multi-Channel Wrap Around Coding
Figure 8-3. ATD Control Register 0 (ATDCTL0)
MC9S12VR Family Reference Manual, Rev. 2.2
Preliminary - Subject to Change Without Notice
Table 8-1. ATDCTL0 Field Descriptions
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
5
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
4
Multiple Channel Conversions (MULT = 1)
Description
Wraparound to AN0 after Converting
WRAP3
Table
1
3
8-2.
Reserved
AN1
AN2
AN3
AN4
AN5
AN5
AN5
AN5
AN5
AN5
AN5
AN5
AN5
AN5
AN5
Analog-to-Digital Converter (ADC12B6CV2)
WRAP2
1
1
2
WRAP1
1
1
WRAP0
1
0
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