mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 533

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mc9s12vr48

Manufacturer Part Number
mc9s12vr48
Description
S12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Appendix E
PLL Electrical Specifications
E.1
E.1.1
E.1.1.1
With each transition of the feedback clock, the deviation from the reference clock is measured and the
input voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt
changes in the VCOCLK frequency. Noise, voltage, temperature and other factors cause slight variations
in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock
periods as illustrated in
The relative deviation of t
number of clock periods (N).
Defining the jitter as:
The following equation is a good fit for the maximum jitter:
Freescale Semiconductor
Reset, Oscillator and PLL
0
Phase Locked Loop
Jitter Information
t
min1
t
nom
t
max1
Figure
nom
1
is at its maximum for one clock period, and decreases towards zero for larger
MC9S12VR Family Reference Manual, Rev. 2.2
E-1..
J N
Preliminary - Subject to Change Without Notice
( )
=
Figure E-1. Jitter Definitions
max 1
2
t
---------------------- -
N t
max
t
minN
t
maxN
nom
( )
N
3
,
1
---------------------- -
N t
t
min
nom
( )
N
N-1
N
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