mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 121

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

4.1.2.2
For S12CPMU_UHV Wait Mode is the same as Run Mode.
4.1.2.3
This mode is entered by executing the CPU STOP instruction.
The voltage regulator is in Reduced Performance Mode (RPM).
The API is available.
The Phase Locked Loop (PLL) is off.
The Internal Reference Clock (IRC1M) is off.
Core Clock, Bus Clock and BDM Clock are stopped.
Depending on the setting of the PSTP and the OSCE bit, Stop Mode can be differentiated between Full
Stop Mode (PSTP = 0 or OSCE=0) and Pseudo Stop Mode (PSTP = 1 and OSCE=1). In addition, the
behavior of the COP in each mode will change based on the clocking method selected by
COPOSCSEL[1:0].
Freescale Semiconductor
•
— The PLLCLK is on and used to qualify the external oscillator clock.
Full Stop Mode (PSTP = 0 or OSCE=0)
External oscillator (XOSCLCP) is disabled.
— If COPOSCSEL1=0:
— If COPOSCSEL1=1:
– Enable the external oscillator (OSCE bit)
– Wait for oscillator to start up (UPOSC=1)
– Select the Oscillator Clock (OSCCLK) as Bus Clock (PLLSEL=0).
The COP and RTI counters halt during Full Stop Mode.
After wake-up from Full Stop Mode the Core Clock and Bus Clock are running on PLLCLK
(PLLSEL=1). COP and RTI are running on IRCCLK (COPOSCSEL0=0, RTIOSCSEL=0).
The clock for the COP is derived from ACLK (trimmable internal RC-Oscillator clock). During
Full Stop Mode the ACLK for the COP can be stopped (COP static) or running (COP active)
depending on the setting of bit CSAD. When bit CSAD is set the ACLK clock source for the
COP is stopped during Full Stop Mode and COP continues to operate after exit from Full Stop
Wait Mode
Stop Mode
The voltage regulator output voltage may degrade to a lower value than in
Full Performance Mode (FPM), additionally the current sourcing capability
is substantially reduced (see also Appendix for VREG electrical
parameters). Only clock source ACLK is available and the Power On Reset
(POR) circuitry is functional. The Low Voltage Interrupt (LVI) and Low
Voltage Reset (LVR) are disabled.
MC9S12VR Family Reference Manual, Rev. 2.2
Preliminary - Subject to Change Without Notice
NOTE
Clock, Reset and Power Management (S12CPMU_UHV)
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