mc9s12vr48 Freescale Semiconductor, Inc, mc9s12vr48 Datasheet - Page 379

• Manufacturer Part Number: mc9s12vr48
• Description: S12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Note: Bits related to available channels have functional effect. Writing to unavailable bits has no effect. Read from unavailable
12.3.2.3
1
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0002
OC7M[7:0]
This register is available only when channel 7 exists and is reserved if that channel does not exist. Writes to a reserved register
have no functional effect. Reads from a reserved register return zeroes.
FOC[7:0]
Reset
Field
Field
7:0
7:0
bits return a zero.
W
R
OC7M7
Force Output Compare Action for Channel 7:0 — A write to this register with the corresponding data bit(s) set
causes the action which is programmed for output compare “x” to occur immediately. The action taken is the
same as if a successful comparison had just taken place with the TCx register except the interrupt flag does not
get set.
Note: A channel 7 event, which can be a counter overflow when TTOV[7] is set or a successful output compare
Output Compare 7 Mask — A channel 7 event, which can be a counter overflow when TTOV[7] is set or a
successful output compare on channel 7, overrides any channel 6:0 compares. For each OC7M bit that is set,
the output compare action reflects the corresponding OC7D bit.
0 The corresponding OC7Dx bit in the output compare 7 data register will not be transferred to the timer port on
1 The corresponding OC7Dx bit in the output compare 7 data register will be transferred to the timer port on a
Note: The corresponding channel must also be setup for output compare (IOSx = 1 and OCPDx = 0) for data to
Output Compare 7 Mask Register (OC7M)
0
7
a channel 7 event, even if the corresponding pin is setup for output compare.
channel 7 event.
on channel 7, overrides any channel 6:0 compares. If forced output compare on any channel occurs at the
same time as the successful output compare then forced output compare action will take precedence and
interrupt flag won’t get set.
be transferred from the output compare 7 data register to the timer port.
OC7M6
0
Figure 12-8. Output Compare 7 Mask Register (OC7M)
6
MC9S12VR Family Reference Manual, Rev. 2.2
Preliminary - Subject to Change Without Notice
Table 12-3. CFORC Field Descriptions
Table 12-4. OC7M Field Descriptions
OC7M5
0
5
OC7M4
0
4
Description
Description
OC7M3
0
3
OC7M2
0
2
Timer Module (TIM16B8CV3)
OC7M1
0
1
OC7M0
0
0
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