ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 97
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Manufacturer
Quantity
Price
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10.5
10.6
10.6.1
8210B–AVR–04/10
Interrupt level
Interrupt priority
Static priority
A return from an interrupt handling routine takes five clock cycles. During these five clock cycles,
the program counter is popped from the stack and the stack pointer is incremented.
The interrupt level is independently selected for each interrupt source. For any interrupt request,
the PMIC also receives the interrupt level for the interrupt. The interrupt levels and their corre-
sponding bit values for the interrupt level configuration of all interrupts is shown in
Table 10-1.
The interrupt level of an interrupt request is compared against the current level and status of the
interrupt controller. An interrupt request on higher level will interrupt any ongoing interrupt han-
dler from a lower level interrupt. When returning from the higher level interrupt handler, the
execution of the lower level interrupt handler will continue.
Within each interrupt level, all interrupts have a priority. When several interrupt requests are
pending, the order of which interrupts are acknowledged is decided both by the level and the pri-
ority of the interrupt request. Interrupts can be organized in a static or dynamic (round-robin)
priority scheme. High and Medium level interrupts and the NMI will always have static priority.
For Low level interrupts, static or dynamic priority scheduling can be selected.
Interrupt vectors (IVEC) are located at fixed addresses. For static priority, the interrupt vector
address decides the priority within one interrupt level where the lowest interrupt vector address
has the highest priority. Refer to the device datasheet for interrupt vector table with the base
address for all modules and peripherals with interrupt. Refer to the interrupt vector summary of
each module and peripheral in this manual for a list of interrupts and their corresponding offset
address within the different modules and peripherals.
Interrupt level
configuration
00
01
10
11
Interrupt level
Group Configuration
MED
OFF
LO
HI
Description
Interrupt disabled.
Low level interrupt
Medium level interrupt
High level interrupt
XMEGA D
Table
10-1.
97