ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 169
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega32D4-AU
Manufacturer:
Atmel
Quantity:
123
Part Number:
ATxmega32D4-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega32D4-CU
Manufacturer:
Maxim
Quantity:
71
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 910
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 704
Part Number:
ATxmega32D4-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
16. TWI – Two Wire Interface
16.1
16.2
8210B–AVR–04/10
Features
Overview
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The Two Wire Interface (TWI) is bi-directional 2-wire bus communication, which is I
SMBus compatible.
A device connected to the bus must act as a master or slave.The master initiates a data transac-
tion by addressing a slave on the bus, and telling whether it wants to transmit or receive data.
One bus can have several masters, and an arbitration process handles priority if two or more
masters try to transmit at the same time.
The TWI module in XMEGA implements both master and slave functionality. The master and
slave functionality are separated from each other and can be enabled separately. They have
separate control and status register, and separate interrupt vectors. Arbitration lost, errors, colli-
sion and clock hold on the bus will be detected in hardware and indicated in separate status
flags available in both master and slave mode.
The master module contains a baud rate generator for flexible clock generation. Both 100 kHz
and 400 kHz bus frequency at low system clock speed is supported. Quick Command and Smart
Mode can be enabled to auto trigger operations and reduce software complexity.
For the slave, 7-bit and general address call recognition is implemented in hardware. 10-bit
addressing is also supported. A dedicated address mask register can act as a second address
match register or as a mask register for the slave address to match on a range of addresses.
The slave logic continues to operate in all sleep modes, including Power down. This enables the
slave to wake up from sleep on TWI address match. It is possible to disable the address match-
ing and let this be handled in software instead. This allows the slave to detect and respond to
several addresses. Smart Mode can be enabled to auto trigger operations and reduce software
complexity.
The TWI module includes bus state logic that collects information to detect START and STOP
conditions, bus collision and bus errors. This is used to determine the bus state (idle, owner,
busy or unknown) in master mode. The bus state logic continues to operate in all sleep modes
including Power down.
Fully Independent Master and Slave Operation
Multi-Master, Single Master, or Slave Only Operation
Phillips I
SMBus compatible
100 kHz and 400 kHz support at low system clock frequencies
Slew-Rate Limited Output Drivers
Input Filter provides noise suppression
7-bit, and General Call Address Recognition in Hardware
Address mask register for address masking or dual address match
10-bit addressing supported
Optional Software Address Recognition Provides Unlimited Number of Slave Addresses
Slave can operate in all sleep modes, including Power Down
Support for Arbitration between START/Repeated START and Data Bit (SMBus)
Slave Arbitration allows support for Address Resolve Protocol (ARP) (SMBus)
2
C compatible
XMEGA D
2
C and
169