ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 207
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Manufacturer
Quantity
Price
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18.7.4
18.7.5
18.8
18.8.1
8210B–AVR–04/10
Asynchronous Data Reception
Disabling the Receiver
Flushing the Receive Buffer
Asynchronous Clock Recovery
A disabling of the Receiver will be immediate. The Receiver buffer will be flushed, and data from
ongoing receptions will be lost.
If the receive buffer has to be flushed during normal operation, read the DATA location until the
Receive Complete Interrupt Flags is cleared.
The USART includes a clock recovery and a data recovery unit for handling asynchronous data
reception. The clock recovery logic is used for synchronizing the incoming asynchronous serial
frames at the RxD pin to the internally generated baud rate clock. The data recovery logic sam-
ples and low pass filters each incoming bit, thereby improving the noise immunity of the
Receiver. The asynchronous reception operational range depends on the accuracy of the inter-
nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.
The clock recovery logic synchronizes internal clock to the incoming serial frames.
on page 207
rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double Speed
mode. The horizontal arrows illustrate the synchronization variation due to the sampling pro-
cess. Note the larger time variation when using the Double Speed mode of operation. Samples
denoted zero are samples done when the RxD line is idle, i.e. no communication activity.
Figure 18-6. Start Bit Sampling
When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the
start bit detection sequence is initiated. Sample 1 denotes the first zero-sample as shown in the
figure. The clock recovery logic then uses samples 8, 9, and 10 for Normal mode, and samples
4, 5, and 6 for Double Speed mode (indicated with sample numbers inside boxes on the figure)
to decide if a valid start bit is received. If two or more of these three samples have a low level
(the majority wins), the start bit is accepted. The clock recovery logic is synchronized and the
data recovery can begin. If two or more of the three samples have a high level the start bit is
rejected as a noise spike and the Receiver starts looking for the next high to low-transition. The
synchronization process is repeated for each start bit.
(U2X = 0)
(U2X = 1)
Sample
Sample
RxD
0
0
IDLE
illustrates the sampling process of the start bit of an incoming frame. The sample
0
1
1
2
3
2
4
5
3
6
7
4
8
START
9
5
10
11
6
12
13
7
14
15
8
XMEGA D
16
1
1
Figure 18-6
2
BIT 0
3
2
207