ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 129
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Manufacturer
Quantity
Price
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12.7.1
8210B–AVR–04/10
Input Capture
Event Source Selection for capture operation
The Event Action setting in the Timer/Counter will determine the type of capture that is done.
The CC channel to use must be enabled individually before capture can be done. When the cap-
ture condition occur, the Timer/Counter will time-stamp the event by copying the current value in
the Count register into the enabled CC channel register.
When an I/O pin is used as event source for the Capture, the pin must be configured for edge
sensing. For details on sense configuration on I/O pins, refer to
page
will be stored in the Most Significant Bit (MSB) of the Capture register after a Capture. If the
MSB of the Capture register is zero, a falling edge generated the Capture. If the MSB is one, a
rising edge generated the Capture.
Three different types of capture are available.
Selecting the input capture event action, makes the enabled capture channel perform an input
capture on any event. The interrupt flags will be set and indicate that there is a valid capture
result in the corresponding CC register. Equally the buffer valid flags indicates valid data in the
buffer registers. Refer to
buffering.
The counter will continuously count for BOTTOM to TOP, then restart on BOTTOM as shown in
Figure
Figure 12-9. Input capture timing
CNT
106. If the Period register value is set lower than 0x8000, the polarity of the I/O pin edge
12-9. The figure also shows four capture events for one capture channel.
events
Event System
TOP
BOT
CH0MUX
CH1MUX
CH7MUX
Capture 0
”Double Buffering” on page 125
Event channel 0
Event channel 1
Event channel 7
Capture 1
Capture 2
Rotate
for more details on capture double
Event Source Selection
”Input Sense Configuration” on
CCA capture
CCB capture
CCC capture
CCD capture
Capture 3
XMEGA D
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