ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 259
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Manufacturer
Quantity
Price
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22.3
22.3.1
8210B–AVR–04/10
PDI Physical
Enabling
Figure 22-1. The PDI with PDI physical and closely related modules (grey)
The PDI physical layer handles the basic low-level serial communication. The physical layer
uses a bi-directional half-duplex synchronous serial receiver and transmitter (as a USART in
USRT mode). The physical layer includes start-of-frame detection, frame error detection, parity
generation, parity error detection, and collision detection.
The PDI is accessed through two pins:
In addition to these two pins, V
grammer/debugger and the device.
Figure 22-2. PDI connection
The remainder of this section is only intended for third parties developing programming support
for XMEGA.
The PDI Physical must be enabled before it can be used. This is done by first forcing the
PDI_DATA line high for a period longer than the equivalent external reset minimum pulse width
PDI_CLK
PDI_DATA
• PDI_CLK: PDI clock input (Reset pin).
• PDI_DATA: PDI data input/output (Test pin).
Program and Debug Interface (PDI)
Gnd
(physical layer)
PDI Physical
Programmer/
Debugger
CC
and GND must also be connected between the External Pro-
Figure 22-2 on page 259
Controller
PDI
Vcc
shows a typical connection.
PDI_CLK (RESET)
PDI_DATA (TEST)
PDIBUS
Internal Interfaces
XMEGA D
Controller
Memories
OCD
NVM
NVM
259