ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 131
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega32D4-AU
Manufacturer:
Atmel
Quantity:
123
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Quantity:
20 000
Company:
Part Number:
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Manufacturer:
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Quantity:
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Company:
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Manufacturer:
Atmel
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1 910
Company:
Part Number:
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Manufacturer:
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Part Number:
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Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
12.7.4
12.7.5
12.8
8210B–AVR–04/10
Compare Channel
32-bit Input Capture
Capture Overflow
Figure 12-11. Pulse-width capture of external signal.
Two Timer/Counters can be used together to enable true 32-bit Input Capture. In a typical 32-bit
Input Capture setup the overflow event of the least significant timer is connected via the Event
System and used as clock input for the most significant timer.
Since all events are pipelined, the most significant timer will be updated one peripheral clock
period after an overflow occurs for the least significant timer. To compensate for this delay the
capture event for the most significant timer must be equally delayed by setting the Event Delay
bit for this timer.
The Timer/Counter can detect buffer overflow on any of the Input Capture Channels. In the case
where both the Buffer Valid flag and Capture Interrupt Flag are set, and a new capture event is
detected there is nowhere to store the new time-stamp. If a buffer overflow is detected the new
value is rejected, the Error Interrupt Flag is set and the optional interrupt is generated.
Each compare channel continuously compares the counter value (CNT) with the CCx register. If
CNT equals CCx the comparator signals a match. The match will set the CC channel's interrupt
flag at the next timer clock cycle, and the event and optional interrupt is generated.
The compare buffer register provides double buffer capability equivalent to the period buffer.
The double buffering synchronizes the update of the CCx register with the buffer value to either
the TOP or BOTTOM of the counting sequence according to the UPDATE condition signal from
the Timer/Counter control logic. The synchronization prevents the occurrence of odd-length,
non-symmetrical PWM/FRQ pulses, thereby making the output glitch-free.
external signal
events
CNT
MAX
BOT
Pulsewitdh (t
p
)
XMEGA D
"capture"
131