ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 143
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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12.11.10 INTFLAGS - Interrupt Flag Register
12.11.11 TEMP - Temporary Register for 16-bit Access
8210B–AVR–04/10
• Bit 7:4 - CCxIF: Compare or Capture Channel x Interrupt Flag
The Compare or Capture Interrupt Flag (CCxIF) is set on a compare match or on an input cap-
ture event on the corresponding CC channel.
For all modes of operation except for capture the CCxIF will be set when a compare match
occurs between the count register (CNT) and the corresponding compare register (CCx). The
CCxIF is automatically cleared when the corresponding interrupt vector is executed.
For input capture operation the CCxIF will be set if the corresponding compare buffer contains
valid data (i.e. when CCxBV is set). The flag will be cleared when the CCx register is read. Exe-
cuting the Interrupt Vector will in this mode of operation not clear the flag.
The flag can also be cleared by writing a one to its bit location.
• Bit 3:2 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 1 - ERRIF: Error Interrupt Flag
The ERRIF is set on multiple occasions depending on mode of operation.
In FRQ or PWM waveform generation mode of operation the ERRIF is set on a fault detect con-
dition from the fault protection feature in the AWeX Extention. For Timer/Counters which do not
have the AWeX extention available, this flag is never set in FRQ or PWM waveform generation
mode.
For capture operation the ERRIF is set if a buffer overflow occurs on any of the CC channels.
For event controlled QDEC operation the ERRIF is set when an incorrect index signal is given.
The ERRIF is automatically cleared when the corresponding interrupt vector is executed. The
flag can also be cleared by writing a one to its bit location.
• Bit 0 - OVFIF: Overflow/Underflow Interrupt Flag
The OVFIF is set either on a TOP (overflow) or BOTTOM (underflow) condition depending on
the WGMODE setting. The OVFIF is automatically cleared when the corresponding interrupt
vector is executed. The flag can also be cleared by writing a one to its bit location.
The TEMP register is used for single cycle 16-bit access to the 16-bit Timer/Counter registers
from the CPU. There is one common TEMP register for all the 16-bit Timer/Counter registers.
Bit
+0x0C
Read/Write
Initial Value
CCDIF
R/W
7
0
CCCIF
R/W
6
0
CCBIF
R/W
5
0
CCAIF
R/W
4
0
R
3
–
0
R
2
–
0
ERRIF
R/W
1
0
XMEGA D
OVFIF
R/W
0
0
INTFLAGS
143