ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 100
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega32D4-AU
Manufacturer:
Atmel
Quantity:
123
Part Number:
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Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega32D4-CU
Manufacturer:
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Quantity:
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Company:
Part Number:
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Manufacturer:
Atmel
Quantity:
1 910
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 704
Part Number:
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Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
10.8.3
10.9
8210B–AVR–04/10
Address
+0x00
+0x01
+0x02
Register Summary
CTRL - PMIC Control Register
Name
STATUS
INTPRI
CTRL
change the priority queue. This register is not reinitialized to its initial value if round-robing
scheduling is disabled, so if default static priority is needed the register must be written to zero.
• Bit 7 - RREN: Round-robin Scheduling Enable
When the RREN bit is set the round-robin scheduling scheme is enabled for low level interrupts.
When this bit is cleared, the priority is static according to interrupt vector address where the low-
est address has the highest priority.
• Bit 6 - IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the Applica-
tion section in flash. When this bit is set (one), the interrupt vectors are moved to the beginning
of the Boot section of the Flash. Refer to the device datasheet for the absolute address.
This bit is protected by the Configuration Change Protection mechanism, refer to
Change Protection” on page 12
• Bit 5:3 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 2 - HILVLEN: High Level Interrupt Enable
When this bit is set all high level interrupts are enabled. If this bit is cleared, high level interrupt
requests will be ignored.
• Bit 1 - MEDLVLEN: Medium Level Interrupt Enable
When this bit is set all medium level interrupts are enabled. If this bit is cleared, medium level
interrupt requests will be ignored.
• Bit 0 - LOLVLEN: Low Level Interrupt Enable
When this bit is set all low level interrupts are enabled. If this bit is cleared, low level interrupt
requests will be ignored.
NMIEX
Bit 7
Bit
+0x02
Read/Write
Initial Value
RREN
Bit 6
IVSEL
RREN
–
R/W
7
0
IVSEL
Bit 5
R/W
6
0
–
–
for details.
R
5
–
0
Bit 4
–
–
INTPRI[7:0]
R
4
–
0
Bit 3
–
–
R
3
–
0
HILVLEX
HILVLEN
Bit 2
HILVLEN
R/W
2
0
MEDLVLEN
MEDLVLEX
Bit 1
MEDLVLEN
R/W
1
0
LOLVLEN
LOLVLEX
XMEGA D
Bit 0
LOLVLEN
R/W
0
0
”Configuration
Page
CTRL
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99
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