ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 16
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega32D4-AU
Manufacturer:
Atmel
Quantity:
123
Part Number:
ATxmega32D4-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATxmega32D4-CU
Manufacturer:
Maxim
Quantity:
71
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 910
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 704
Part Number:
ATxmega32D4-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
3.14.8
3.14.9
8210B–AVR–04/10
SPH - Stack Pointer Register High
SREG - Status Register
Note:
• Bit 7:0 - SP[7:0]: Stack Pointer Register Low byte
These bits hold the 8 LSB of the 16-bits Stack Pointer (SP).
Note:
• Bits 7:0 - SP[15:8]: Stack Pointer Register High byte
These bits hold the 8 MSB of the 16-bits Stack Pointer (SP).
The Status Register (SREG) contains information about the result of the most recently executed
arithmetic or logic instruction.
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for interrupts to be enabled. If the Global Interrupt
Enable Register is cleared, none of the interrupts are enabled independent of the individual
interrupt enable settings. The I-bit is not cleared by hardware after an interrupt has occurred.
The I-bit can be set and cleared by the application with the SEI and CLI instructions, as
described in the “Instruction Set Description”.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions Bit Load (BLD) and Bit Store (BST) use the T-bit as source or destina-
tion for the operated bit. A bit from a register in the Register File can be copied into T by the BST
instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD
instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag (H) indicates a Half Carry in some arithmetic operations. Half Carry Is useful
in BCD arithmetic. See the “Instruction Set Description” for detailed information.
Bit
+0x0D
Read/Write
Initial Value
Bit
+0x0E
Read/Write
Initial Value
Bit
+0x0F
Read/Write
Initial Value
(1)
1. Refer to specific device datasheets for exact initial values.
1. Refer to specific device datasheets for exact initial values.
(1)
R/W
R/W
R/W
7
0
0/1
I
0/1
7
7
R/W
R/W
R/W
0/1
0/1
T
6
0
6
6
R/W
R/W
R/W
0/1
0/1
H
5
5
5
0
R/W
R/W
0/1
0/1
R/W
4
4
S
4
0
SP[15:8]
SP[7:0]
R/W
R/W
0/1
0/1
3
R/W
3
3
V
0
R/W
R/W
0/1
0/1
2
2
R/W
2
N
0
R/W
0/1
R/W
0/1
1
1
R/W
Z
1
0
XMEGA D
R/W
0/1
R/W
0/1
0
0
R/W
C
0
0
SPH
SPL
SREG
16