ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 200
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ATxmega32D4
Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega32D4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega32D4-AU
Manufacturer:
Atmel
Quantity:
123
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Manufacturer:
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Quantity:
20 000
Company:
Part Number:
ATxmega32D4-CU
Manufacturer:
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Quantity:
71
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
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1 910
Company:
Part Number:
ATxmega32D4-MH
Manufacturer:
Atmel
Quantity:
1 704
Part Number:
ATxmega32D4-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
8210B–AVR–04/10
Figure 18-1. USART Block Diagram
The Clock Generation logic has a fractional baud rate generator that is able to generate a wide
range of USART baud rates. It also includes synchronization logic for external clock input in syn-
chronous slave operation.
The Transmitter consists of a single write buffer (DATA), a shift register, Parity Generator and
control logic for handling different frame formats. The write buffer allows continuous data trans-
mission without any delay between frames.
The Receiver consists of a two level FIFO receive buffer (DATA), and a shift register. Data and
clock recovery units ensure robust synchronization and noise filtering during asynchronous data
reception. It includes frame error, buffer overflow and parity error detection.
When the USART is set in Master SPI compliant mode, all USART specific logic is disabled,
leaving the transmit and receive buffers, shift registers, and Baud Rate Generator enabled. Pin
control and interrupt generation is identical in both modes. The registers are used in both
modes, but the functionality differs for some control settings.
An IRCOM Module can be enabled for one USART to support IrDA 1.4 physical compliant pulse
modulation and demodulation for baud rates up to 115.2 kbps. For details refer to
Communication Module” on page 220
CTRLA
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
BAUD RATE GENERATOR
FRACTIONAL DEVIDE
for details.
DATA (Transmit)
DATA (Receive)
BSEL [H:L]
CTRLB
GENERATOR
SYNC LOGIC
RECOVERY
RECOVERY
CHECKER
PARITY
CLOCK
PARITY
DATA
OSC
Clock Generator
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
Transmitter
PIN
PIN
PIN
TX
RX
Receiver
CTRLC
XMEGA D
XCK
RxD
TxD
”IRCOM - IR
200